Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
LIST OF FIGURES
Figure 3.1 - COM20019I 3V OPERATION ...................................................................................................................11
Figure 5.1 - MULTIPLEXED, 8051-LIKE BUS INTERFACE WITH RS-485 INTERFACE ............................................17
Figure 5.2 - NON-MULTIPLEXED, 6801-LIKE BUS INTERFACE WITH RS-485 INTERFACE ...................................18
Figure 5.3 - HIGH SPEED CPU BUS TIMING - INTEL CPU MODE............................................................................19
Figure 5.4 - COM20019I 3V NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS .....................................21
Figure 5.5 - INTERNAL BLOCK DIAGRAM ..................................................................................................................23
Figure 6.1 - SEQUENTIAL ACCESS OPERATION ......................................................................................................36
Figure 6.2 - RAM BUFFER PACKET CONFIGURATION .............................................................................................39
Figure 6.3 - COMMAND CHAINING STATUS REGISTER QUEUE ..............................................................................41
Figure 7.1 - AC MEASUREMENTS ..............................................................................................................................49
Figure 8.1 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE .................................................50
Figure 8.2 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE .................................................51
Figure 8.3 - MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE................................................52
Figure 8.4 - MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE................................................53
Figure 8.5 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................54
Figure 8.6 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................55
Figure 8.7 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................56
Figure 8.8 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; READ CYCLE ........................................57
Figure 8.9 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE ......................................58
Figure 8.10 - NON-MULTIPLEXED BUS, 80XX-LIKE CONTROL SIGNALS; WRITE CYCLE ....................................59
Figure 8.11 - NON-MULTIPLEXED BUS, 68XX-LIKE CONTROL SIGNALS; WRITE CYCLE ....................................61
Figure 10.1 - EFFECT OF THE EB BIT ON THE TA/RI BIT ........................................................................................67
Figure 11.1 - EXAMPLE OF INTERFACE CIRCUIT DIAGRAM TO ISA BUS .............................................................69
LIST OF TABLES
Table 5.1 - Typical Media .............................................................................................................................................24
Table 6.1 - Read Register Summary.............................................................................................................................25
Table 6.2 - Write Register Summary ............................................................................................................................26
Table 6.3 - Status Register ...........................................................................................................................................29
Table 6.4 - Diagnostic Status Register..........................................................................................................................30
Table 6.5 - Command Register.....................................................................................................................................31
Table 6.6 - Address Pointer High Register ....................................................................................................................32
Table 6.7 - Address Pointer Low Register.....................................................................................................................32
Table 6.8 - Sub Address Register .................................................................................................................................33
Table 6.9 - Configuration Register ................................................................................................................................33
Table 6.10 - Setup 1 Register .......................................................................................................................................34
Table 6.11 - Setup 2 Register .......................................................................................................................................35
SMSC COM20019I 3.3V Rev.C
Page 5
Rev. 10-31-06
DATASHEET
SMSC [ SMSC CORPORATION ]
