Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
RAM
6.6.1
Internal Reset Logic................................................................................................................................43
Bus Determination ..................................................................................................................................43
Normal Results: ......................................................................................................................................45
Abnormal Results: ..................................................................................................................................45
6.7
6.8
6.9
7.1
7.2
INITIALIZATION SEQUENCE ....................................................................................................... 43
6.7.1
6.8.1
6.8.2
IMPROVED DIAGNOSTICS .......................................................................................................... 44
OSCILLATOR ................................................................................................................................ 45
Chapter 7
Operational Description .................................................................................................... 47
MAXIMUM GUARANTEED RATINGS* ......................................................................................... 47
DC ELECTRICAL CHARACTERISTICS........................................................................................ 47
Chapter 8
Chapter 9
9.1
9.2
10.1
10.2
Timing Diagrams................................................................................................................ 50
Package Outlines ................................................................................................................ 64
28 Pin PLCC Package Outline and Parameters ............................................................................ 64
48 Pin TQFP Package Outline and Parameters ............................................................................ 65
Chapter 10
Appendix A...................................................................................................................... 66
NOSYNC Bit................................................................................................................................... 66
EF Bit.............................................................................................................................................. 66
Chapter 11
Chapter 12
12.1
Appendix B ...................................................................................................................... 69
Appendix C...................................................................................................................... 70
Software Identification of the COM20019I 3V Rev B and Rev C................................................... 70
Rev. 10-31-06
Page 4
SMSC COM20019I 3.3V Rev.C
DATASHEET
SMSC [ SMSC CORPORATION ]
