Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM
Chapter 3
PIN NO
PLCC
TQFP
1, 2,
44, 45,
3
46
NAME
Address
0-2
Description of Pin Functions
SYMBOL
A0/nMUX
A1
A2/ALE
AD0-AD2,
D3-D7
I/O
DESCRIPTION
MICROCONTROLLER INTERFACE
On a non-multiplexed mode, A0-A2 are address
IN
input bits. (A0 is the LSB) On a multiplexed
IN
address/data bus, nMUX tied Low, A1 is left open,
and ALE is tied to the Address Latch Enable signal.
A1 is connected to an internal pull-up resistor.
IN
On a non-multiplexed bus, these signals are used
I/O
as the lower byte data bus lines. On a multiplexed
address/data bus, AD0-AD2 act as the address
lines (latched by ALE) and as the low data lines.
D3-D7 are always used for data only. These signals
are connected to internal pull-up resistors.
IN
nWR is for 80xx CPU, nWR is Write signal input.
Active Low.
DIR is for 68xx CPU, DIR is Bus Direction signal
input. (Low: Write, High: Read.)
IN
nRD is for 80xx CPU, nRD is Read signal input.
Active Low.
nDS is for 68xx CPU, nDS is Data Strobe signal
input. Active Low.
Hardware reset signal. Active Low.
IN
Interrupt signal output. Active Low.
OUT
Chip Select input. Active Low.
IN
IN
Read and Write Bus Access Timing mode selecting
signal. Status of this signal effects CPU Timing.
L: High speed timing mode (only for non-
multiplexed bus)
H: Normal timing mode
This signal is connected to internal pull-up registers.
NOTE:
BUSTMG pin does not exist in PLCC package.
4, 5, 6,
8, 9,
10, 11,
12
26
1, 2, 4,
7, 9, 10,
12, 13
Data 0-7
37
nWrite/
Direction
nWR/DIR
27
39
nRead/
nData
Strobe
nReset In
nInterrupt
nChip
Select
Read/Write
Bus Timing
Select
nRD/nDS
23
24
25
-
31
34
36
26
nRESET
nINTR
nCS
BUSTMG
SMSC COM20019I 3.3V Rev.C
Page 9
Rev. 10-31-06
DATASHEET
SMSC [ SMSC CORPORATION ]
