Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip
RAM
PIN NO
NAME
SYMBOL
I/O
DESCRIPTION
PLCC
TQFP
TRANSMISSION MEDIA INTERFACE
In Normal Mode, these active low signals carry the
18
24
nPulse 1
nPULSE1
OUT
transmit data information, encoded in pulse format
as DIPULSE waveform. In Backplane Mode, the
nPULSE1 signal driver is programmable (push/pull
or open-drain), while the nPULSE2 signal provides
a clock with frequency of doubled data rate.
nPULSE1 is connected to a weak internal pull-up
resistor on the open/drain driver in backplane
mode.
19
25
nPulse 2
nPULSE2
I/O
This signal carries the receive data information from
the line transceiver.
Transmission Enable signal. Active polarity is
programmable through the nPULSE2 pin.
20
21
28
29
Receive In
RXIN
IN
nTransmit
Enable
nTXEN
OUT
nPULSE2 floating before power-up;
nTXEN active low
nPULSE2 grounded before power-up;
nTXEN active high (this option is only available in
Back Plane mode)
An external crystal should be connected to these
pins. Oscillation frequency range is from 10 MHz to
20 MHz. If an external TTL clock is used instead, it
must be connected to XTAL1 with a 390ohm pull-up
resistor, and XTAL2 should be left floating.
+3.3 Volt power supply pins.
16
17
21
22
Crystal
Oscillator
XTAL1
XTAL2
IN
OUT
15, 28
8, 20,
32, 43
6, 11,
18, 23,
30, 41
3, 5,
Power
Supply
VDD
VSS
PWR
PWR
Ground pins.
7, 14,
22
Ground
Non-connection
13
N/C
N/C
14-17,
19, 27,
33, 35,
38, 40,
42, 47,
48
Rev. 10-31-06
Page 10
SMSC COM20019I 3.3V Rev.C
DATASHEET
SMSC [ SMSC CORPORATION ]
