COM20019I3V-HT 参数 Datasheet PDF下载

Cost Competitive ARCNET (ANSI 878.1) Controller with 2K x 8 On-Chip RAM

TABLE OF CONTENTS

Chapter 1

Chapter 2

Chapter 3

Chapter 4

4.1

4.2

4.3

4.4

4.5

General Description ............................................................................................................. 6

Pin Configurations ............................................................................................................... 7

Description of Pin Functions ............................................................................................... 9

Protocol Description........................................................................................................... 12

NETWORK PROTOCOL................................................................................................................ 12

DATA RATES................................................................................................................................. 12

NETWORK RECONFIGURATION ................................................................................................ 12

BROADCAST MESSAGES............................................................................................................ 13

EXTENDED TIMEOUT FUNCTION............................................................................................... 13

4.5.1

4.5.2

4.5.3

Response Time.......................................................................................................................................13

Idle Time.................................................................................................................................................13

Reconfiguration Time..............................................................................................................................14

Invitations To Transmit ...........................................................................................................................14

Free Buffer Enquiries..............................................................................................................................14

Data Packets ..........................................................................................................................................15

Acknowledgements.................................................................................................................................15

Negative Acknowledgements .................................................................................................................15

4.6

LINE PROTOCOL .......................................................................................................................... 14

4.6.1

4.6.2

4.6.3

4.6.4

4.6.5

Chapter 5

5.1

5.2

5.1.1

5.2.1

5.2.2

5.2.3

System Description............................................................................................................. 16

High Speed CPU Bus Timing Support ....................................................................................................19

Backplane Configuration.........................................................................................................................21

Differential Driver Configuration..............................................................................................................22

Programmable TXEN Polarity.................................................................................................................22

MICROCONTROLLER INTERFACE ............................................................................................. 16

TRANSMISSION MEDIA INTERFACE.......................................................................................... 21

Chapter 6

6.1

6.2

6.2.1

6.2.2

6.2.3

6.2.4

6.2.5

6.2.6

6.2.7

6.2.8

6.2.9

6.2.10

6.2.11

6.2.12

6.2.13

Functional Description....................................................................................................... 25

Interrupt Mask Register (IMR) ................................................................................................................26

Data Register..........................................................................................................................................27

Tentative ID Register ..............................................................................................................................27

Node ID Register ....................................................................................................................................27

Next ID Register .....................................................................................................................................27

Status Register .......................................................................................................................................27

Diagnostic Status Register .....................................................................................................................28

Command Register.................................................................................................................................28

Address Pointer Registers ......................................................................................................................28

Configuration Register ........................................................................................................................28

Sub-Address Register .........................................................................................................................28

Setup 1 Register .................................................................................................................................28

Setup 2 Register .................................................................................................................................29

Sequential Access Memory ....................................................................................................................36

Access Speed.........................................................................................................................................37

Selecting RAM Page Size.......................................................................................................................37

Transmit Sequence.................................................................................................................................39

Receive Sequence..................................................................................................................................40

Transmit Command Chaining .................................................................................................................42

Receive Command Chaining ..................................................................................................................42

MICROSEQUENCER .................................................................................................................... 25

INTERNAL REGISTERS................................................................................................................ 26

6.3

6.4

INTERNAL RAM ............................................................................................................................ 36

6.3.1

6.3.2

6.4.1

6.4.2

6.4.3

SOFTWARE INTERFACE .............................................................................................................37

6.5

6.6

COMMAND CHAINING.................................................................................................................. 41

6.5.1

6.5.2

RESET DETAILS ........................................................................................................................... 43

Page 3

Rev. 10-31-06

SMSC COM20019I 3.3V Rev.C

DATASHEET