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CAP1128-1-BP-TR 参数 Datasheet PDF下载

CAP1128-1-BP-TR图片预览
型号: CAP1128-1-BP-TR
PDF下载: 下载PDF文件 查看货源
内容描述: [LED Driver]
分类和应用: 驱动接口集成电路
文件页数/大小: 88 页 / 585 K
品牌: SMSC [ SMSC CORPORATION ]
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8 Channel Capacitive Touch Sensor with 2 LED Drivers  
Datasheet  
tP  
tHIGH  
tLOW  
SPI_CLK  
tFALL  
tRISE  
tSU:DAT  
SPI_MSIO or  
SPI_MOSI or  
SPI_MISO  
tD:CLK  
tHD:DAT  
Figure 3.2 SPI Timing  
3.5.1  
SPI Normal Mode  
The SPI Bus can operate in two modes of operation, normal and bi-directional mode. In the normal  
mode of operation, there are dedicated input and output data lines. The host communicates by sending  
a command along the CAP1128 SPI_MOSI data line and reading data on the SPI_MISO data line.  
Both communications occur simultaneously which allows for larger throughput of data transactions.  
All basic transfers consist of two 8 bit transactions from the Master device while the slave device is  
simultaneously sending data at the current address pointer value.  
Data writes consist of two or more 8-bit transactions. The host sends a specific write command  
followed by the data to write the address pointer. Data reads consist of one or more 8-bit transactions.  
The host sends the specific read data command and continues clocking for as many data bytes as it  
wishes to receive.  
3.5.2  
SPI Bi-Directional Mode  
In the bi-directional mode of operation, the SPI data signals are combined into the SPI_MSIO line,  
which is shared for data received by the device and transmitted by the device. The protocol uses a  
simple handshake and turn around sequence for data communications based on the number of clocks  
transmitted during each phase.  
All basic transfers consist of two 8 bit transactions. The first is an 8 bit command phase driven by the  
Master device. The second is by an 8 bit data phase driven by the Master for writes, and by the  
CAP1128 for read operations.  
The auto increment feature of the address pointer allows for successive reads or writes. The address  
pointer will return to 00h after reaching FFh.  
3.5.3  
SPI_CS# Pin  
The SPI Bus is a single master, multiple slave serial bus. Each slave has a dedicated CS pin (chip  
select) that the master asserts low to identify that the slave is being addressed. There are no formal  
addressing options.  
Revision 1.32 (01-05-12)  
SMSC CAP1128  
DATA2S2HEET