Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Appendix A High-Performance 8051 Cycle Timing
and Instruction Set
The high-performance 8051 processor offers increased performance by executing instructions in a 4-
clock cycle, as opposed to the standard 8051. The shortened bus timing improves the instruction
execution rate for most instructions by a factor of three over the standard 8051 architectures.
Some instructions require a different number of instruction cycles on the high-performance 8051than
they do on the standard 8051. In the standard 8051, all instructions except for MUL and DIV take one
or two instruction cycles to complete. In the high-performance 8051 architecture, instructions can take
between one and five instructions to complete. The average speed improvement for the entire
instruction set is approximately 2.5X.
Table A.1 Legend for Instruction Set Table
SYMBOL
FUNCTION
A
Accumulator
Rn
Register R7-R0
direct
@Ri
rel
Internal register address
Internal register pointed to by R0 or R1 (except MOVX)
Two’s complement offset byte
Direct bit address
bit
#data
8-bit constant
#data 16
addr 16
addr 11
16-bit constant
16-bit destination address
11-bit destination address
Table A.2 8051 Instruction Set
BYTE
INSTRUCTION
CYCLES
HEX
INSTRUCTION
DESCRIPTION
COUNT
CODE
ARITHMETIC
ADD A, Rn
Add register to A
1
2
1
2
1
2
1
2
1
2
1
2
1
2
1
2
28-2F
25
ADD A, direct
ADD A, @Ri
ADD A, #data
ADDC A, Rn
ADDC A, direct
ADDC A, @Ri
ADDC A, #data
Add direct byte to A
Add data memory to A
Add immediate to A
26-27
24
Add register to A with carry
38-3F
35
Add direct byte to A with carry
Add data memory to A with carry
Add immediate to A with carry
36-37
34
SMSC LPC47N350
309
Revision 1.1 (01-14-03)
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