SL74LV374
AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns)
Test
VCC
V
,
Limits
-40 C to
85
min max min max min max
Symbol
Parameter
conditions
25°C
°
°
125°C
Unit
C
tPHL, tPLH
from CP to Qn delay
Propagation
Figure 1
1.2
2.0
3.0
-
-
-
180
45
27
-
-
-
230
56
34
-
-
-
270
68
41
ns
tPHZ tPLZ
from OE to Qn delay
Propagation
Figure 3
Figure 3
Figure 1
1.2
2.0
3.0
-
-
-
160
38
25
-
-
-
200
57
36
-
-
-
240
68
43
tPZH tPZL
from OE to Qn delay
Propagation
1.2
2.0
3.0
-
-
-
160
38
23
-
-
-
200
48
29
-
-
-
240
58
35
tTHL, tTLH
HIGH-to-LOW
1.2
2.0
3.0
-
-
-
75
16
10
-
-
-
100
20
13
-
-
-
120
24
15
and LOW-to-
HIGH transition
time
tW
tSU
tH
Clock pulse
width HIGH or
LOW
Figure 1
1.2 250
-
-
-
350
23
14
-
-
-
540
28
17
-
-
-
2.0
3.0
18
11
Set-up time Dn Figure 2
to CP
1.2
2.0
3.0
45
13
8
-
-
-
50
17
10
-
-
-
100
20
12
-
-
-
Hold time Dn to Figure 2
CP
1.2
2.0
3.0
25
5
5
-
-
-
25
5
5
-
-
-
25
5
5
-
-
-
fc
CI
CP naximum
pulse frequency
Figure 1
2.0
3.0
-
-
27
46
-
-
22
37
-
-
18
31
MHz
pF
Input
3.0
-
7
-
-
-
-
capacitance
CPD
Power
VI = 0 V or VCC 3.0
-
34
-
-
-
-
dissipation
capacitance (per
flip-flop)
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
