SL74LV374
OCTAL D-TIME FLIP-FLOP; POSITIVE EDGE-
TRIGGER (3-StatE)
SL74LV374 are compatible by pinning with SL74HC374 and
SL74HCT374 series. Input voltage levels are compatible with
standard CMOS levels.
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Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS.
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Supply voltage range from 2.0 to 3.2 V
LOW input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ
Output current 8 mÀ
Latch current value not less than 150 mÀ at Ò = 125 °Ñ
ESD acceptable values: not less than 2000 V as per HBM,
and not less than 200 V as per MM
ORDERING INFORMATION
SL74LV374N Plastic DIP
SL74LV374D SOIC
TA = -40° to 125° C
for all packages
BLOCK DIAGRAM
03
04
02
05
D0
D1
D2
D3
D4
D5
D6
D7
CP
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN ASSIGNMENT
07
08
06
09
12
OE 01
20
19
18
VCC
Q0
D0
Q7
D7
02
03
13
14
D1 04
17 D6
15
16
Q1
Q2
Q6
Q5
05
06
16
15
374
17
18
19
D2 07
14 D5
D3
D4
08
09
13
12
11
11
01
Q3
Q4
GND 10
CP
OE
Pin 20=VCC
Pin 10 = GND
FUNCTION TABLE
Inputs
Output
OE
L
L
L
H
CP
Dn
H
L
X
X
Qn
H
L
no change
Z
L, H,
X
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
