SL74LV373
AC CHARACTERISTICS (CL=50 pF, tLH = tHL = 6.0 ns)
Test
VCC
V
,
Limits
C to 85
min max min max min
Symbol
Parameter
conditions
25°C
-40°
°C
125
°
C
Unit
max
tPHL, tPLH
from Dn to Qn
Propagation delay Figure 1
Propagation delay Figure 2
1.2
2.0
3.0
-
-
-
150
38
23
-
-
-
190
48
29
-
-
-
220
58
35
ns
tPHL, tPLH
from LE to Qn
1.2
2.0
3.0
-
-
-
180
45
27
-
-
-
230
56
34
-
-
-
270
68
41
tPHZ tPLZ
from OE to Qn enable time
3-state output
Figure 4
Figure 4
1.2
2.0
3.0
-
-
-
160
35
23
-
-
-
200
43
28
-
-
-
240
45
32
tPZH tPZL
from OE to Qn time
3-state disable
1.2
2.0
3.0
-
-
-
160
40
24
-
-
-
200
50
30
-
-
-
240
60
36
tTHL, tTLH
HIGH-to-LOW and Figures 1,2
LOW-to-HIGH
transition time
1.2
2.0
3.0
-
-
-
75
16
10
-
-
-
100
20
13
-
-
-
120
24
15
tW
tSU
tH
Clock pulse width Figure 2
HIGH or LOW
1.2 250
-
-
-
350
34
20
-
-
-
450
41
24
-
-
-
2.0
3.0
30
18
Set-up time Dn to Figure 3
LE
1.2
2.0
3.0
45
15
9
-
-
-
50
17
10
-
-
-
100
15
12
-
-
-
Hold time Dn to
LE
Figure 3
1.2
2.0
3.0
25
5
5
-
-
-
25
5
5
-
-
-
25
5
5
-
-
-
CI
Input capacitance
3.0
3.0
-
-
7
-
-
-
-
-
-
-
-
pF
CPD
Power dissipation VI = 0 V or
80
capacitance (per
flip-flop)
VCC
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
