SL74LV373
OCTAL D-TYPE TRANSPARENT LATCH
(3-State)
SL74LV373 are compatible by pinning with SL74HC373 and
SL74HCT373 series. Input voltage levels are compatible with
standard CMOS levels.
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Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
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Voltage supply range: 2.0 to 3.2 V
LOW input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ
Input current LOW/HIGH: 8 mÀ
Latch current: not less than 150 mÀ at Ò = 125 °Ñ
ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM
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ORDERING INFORMATION
SL74LV373N Plastic DIP
SL74LV373D SOIC
TA = -40° to 125° C
for all packages
BLOCK DIAGRAM
03
04
02
05
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
PIN ASSIGNMENT
OE
Q0
VCC
Q7
01
02
03
04
05
06
07
08
09
10
20
19
18
17
16
15
14
13
12
11
07
08
06
09
12
D0
D1
D7
D6
Q6
Q5
D5
D4
Q4
LE
13
14
Q1
15
16
373
Q2
17
18
D2
19
D3
Q3
11
01
GND
LE
OE
Pin 20=VCC
Pin 10 = GND
FUNCTION TABLE
Inputs
Output
OE
LE
Dn
Qn
L
L
L
H
H
L
H
L
X
X
H
L
no change
Z
H
X
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
