SL74LVU04
CHIP PAD DIAGRAM SL74LVU04
1.33 ±0.03
11
13
14
10
12
09
08
07
01
02
04
05
06
03
Chip marking
IN74LVU04
(x=0.130; y=0.130
)
Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer)
Thickness of chip 0.46 ± 0,02 mm
PAD LOCATION
Pad No
01
Symbol
A1
Y1
X
Y
0.130
0.130
0.381
0.616
0.881
1.116
1.115
1.115
1.115
0.804
0.569
0.378
0.143
0.130
0.463
0.230
0.126
0.126
0.126
0.126
0.631
0.846
1.181
1.194
1.194
1.194
1.194
0.813
02
03
A2
Y2
04
05
A3
Y3
06
07
GND
Y4
08
09
A4
Y5
10
11
A5
Y6
12
13
A6
VCC
14
System Logic
6
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
