SL74LVU04
V
min
-
max
0.1
min
-
max
1.0
min
max
1.0
IIH
High-Level
Input Leakage
Current
V = VÑÑ
I
5.5
-
ICC
Quiescent
V =0 Â or VÑÑ
I
5.5
-
4.0
-
20
-
40
ì A
Supply Current
(per Package)
IO = 0 ì A
ICC1
Additional
Quiescent
V = VÑÑ - 0.6V 2.7
-
-
0.2
0.2
-
-
0.5
0.5
-
-
0.85
0.85
mA
I
3.6
Supply Current
on input
-
AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tLH =tHL = 2.5 ns, RL=1 kÙ)
Guaranteed Limit
VCC
Test
Conditions
Symbol
Parameter
25°C
-40°C ¸ 85°C
-40°C ¸ 125°C
Unit
ns
V
Min
max
min
max
min
max
V =0 V or
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I
tPHL (tPLH)
Propagation
Delay, Input A
to Output Y
(Figure 1 )
1.2
2.0
2.7
3.0
4.5
70
22
16
13
11
80
26
19
15
13
100
31
23
18
16
V
1
tLH = tHL
=2.5 ns
Ñ = 50 pF
L
RL = 1 kÙ
-
7.0
-
-
-
-
CI
Input
Capacitance
5.5
pF
pF
CPD
Power Dissipation Capacitance (Per Inverter)
Ò =25°Ñ, V =0V or VCC
À
I
36
Used to determine the no-load dynamic power consumption:
PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz)
(CLVCC2fo) – sum of the outputs
System Logic
4
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
