SL74LV573
AC CHARACTERISICS (CL=50 pF, RL=1 KW, tLH = tHL = 2.5 ns)
Sym
bol
Conditions
Vcc
Limits
+85
Min Max Min Max Min Max
Parameter
-40 to +25
°C
°C
+125
°C
Unit
tPHL/PLH
tPHL/PLH
tPZH/PZL
tPHZ/PLZ
tW
Propagation
delay Dn to
Qn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
-
-
-
-
150
30
23
18
15
-
-
-
-
-
160
39
29
23
19
-
-
-
-
-
170
49
36
29
24
ns
Propagation
delay LE to
Qn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
-
-
-
-
160
34
28
20
17
-
-
-
-
-
180
43
31
25
21
-
-
-
-
-
190
53
34
31
26
ns
ns
ns
ns
ns
ns
3-state
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
-
-
-
-
140
28
22
17
14
-
-
-
-
-
160
37
28
22
18
-
-
-
-
-
170
48
35
28
23
output enable
time OE to
Qn
3-state
outpiut
disable time
OE to Qn
1.2
2.0
2.7
3.0
4.5
VI = Vcc or
GND
-
-
-
-
-
160
31
23
20
17
-
-
-
-
-
160
39
29
24
20
-
-
-
-
-
170
48
36
29
24
LE pulse
width HIGH
1.2
2.0
2.7
3.0
4.5
100
29
21
17
15
-
-
-
-
-
125
34
25
20
18
-
-
-
-
-
150
41
30
24
21
-
-
-
-
-
tsu
Setup time
Dn to LE
1.2
2.0
2.7
3.0
4.5
50
15
11
8
-
-
-
-
-
75
17
13
10
8
-
-
-
-
-
100
20
15
12
10
-
-
-
-
-
6
th
Hold time Dn
to LE
1.2
2.0
2.7
3.0
4.5
40
8
8
8
8
-
-
-
-
-
40
8
8
8
8
-
-
-
-
-
40
8
8
8
8
-
-
-
-
-
CI
Input
capacitance
5.0
Ò=+25 îÑ
7.0
-
ns
ns
CPD
Power
5.5
Ò=+25 îÑ
VI = Vcc or
GND
52
-
dissipation
capacitance
per package
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
