SL74LV573
OCTAL D-TYPE TRANSPARENT LATCH (3-State)
By pinning SL74LV573 are compatible with SL74HC573 and
SL74HCT573 series. Input voltage levels are compatible with
stadard CMOS levels.
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Output voltage levels are compatible with input levels of CMOS,
NMOS and TTL ICS
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Voltage supply range from 1.2 to 5.5 V
LOW input current: 1.0 mÀ; 0.1 mÀ at Ò = 25 °Ñ
Output current 8 mÀ
Latch current: not less than150 mÀ at Ò = 125 °Ñ
ESD acceptable value: not less than 2000 V as per HBM and
not less than 200 V as per MM
ORDERING INFORMATION
SL74LV573N Plastic DIP
SL74LV573D SOIC
TA = -40° to 125° C
for all packages
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Outputs
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
7
8
9
20
19 Q0
18
VCC
OE
L
LE
H
H
L
D
H
L
Q
Q1
H
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
L
L
no change
Z
L
X
X
H
X
H -HIGH voltage level
L - LOW voltage level
X - don’ t care
Z - High impedance state
GND 10
11
LE
System Logic
Semiconductor
SLS
SLS [ SYSTEM LOGIC SEMICONDUCTOR ]
