ST7920
Timing Diagram for checking HCGROM (TT1=1, TT2=0)
The ST7920 check sum process: (DDRAM must be cleared by 0x00 before this process)
In the first place: Resetting the internal counter (set TT1 and TT2 to Height)
In the second place: Setting CGROM mode (set TT1 to Height, TT2 to Low).
In the third place: CLK starts to count 10242 times.
In the final place: Finishing the counting, read the last four bytes to CHECK SUM (reading only when the CLK is
Height).
ST7920 check sum circuit: Data is available when CLK is height; if CLK is low then the data is always FFH. The last
four bytes are Y0, Y1, Y2, and Y3.
The fatest execution time is: tCYC=2us (0.5MHz at 5V).
The table below is a comparing table of HCGROM for different versions.
Version
(Font)
HCGROM last four bytes
Y0
B5
Y1
11
Y2
B5
Y3
11
1
2
Big5 (0A)
GB (0B)
0C
B5
B5
11
11
B5
B5
11
11
3
V4.0
29/49
2008/08/18
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
