ST7920
Serial interface:
ST7920 is in serial interface mode when pulling down PSB pin. Two pins (SCLK and SID) are used to complete the
data transfer. Only write data is available in the serial interface mode.
When chip select (CS) is low, ST7920 serial clock counter and serial data will be reset. Serial transfer counter is set
to the first bit and data register is cleared. After CS is “L”, any further change on SID or SCLK is not allowed. It is
recommended to keep SCLK at “L” and SID at the last status before set CS to “L”. For a minimal system with only
one ST7920 and one MPU, only SCLK and SID pins are necessary. CS pin should pull to high.
ST7920’s serial clock (SCLK) is asynchronous to the internal clock and is generated by MPU. When multiple
instruction/data is transferred, the instruction execution time must be considered. MPU must wait till the previous
instruction is finished and then send the next instruction. ST7920 has no internal instruction buffer area.
When starting a transmission, a start byte is required. It consists of 5 consecutive “1” (sync character). Serial transfer
counter will be reset and synchronized. Followed by 2-bit flag that indicates: read/write (RW) and register/data
selected (RS) operation. Last 4 bits are filled by “0”.
After receiving the sync character, RW and RS bits, every 8 bits instruction/data will be separated into 2 groups.
Higher 4 bits (DB7~DB4) will be placed in the first section followed by 4 “0”s. And lower 4 bits (DB3~DB0) will be
placed in the second section followed by 4 “0”s.
CS
1
1
2
1
3
1
4
1
5
1
6
7
8
0
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
SCLK
SID
RW RS
D7 D6 D5 D4
0
0
0
0
D3 D2 D1 D0
0
0
0
0
Synchronizing
Bit string
Higher
data
Lower
data
1st byte
2nd byte
Timing Diagram of Serial Mode Data Transfer
V4.0
26/49
2008/08/18
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
