ST7669V
8 RESET CIRCUIT
The registers that are initialized are listed below.
Item
After Power On
After Hardware Reset
After Software Reset
Frame memory (RAM data)
RDDID
Random
TBD
No Change
TBD
No Change
TBD
RDDPM
08h
08h
08h
RDDMADCTR
00h
00h
No Change
No Change
00h
RDDCOLMOD
RDDIM
06h (18-Bit/Pixel)
00h
06h (18-Bit/Pixel)
00h
RDDSM
00h
00h
00h
RDDSDR
00h
00h
00h
Sleep In/Out
In
In
In
Display mode (normal/partial)
Display Inversion On/Off
All Pixel Off mode
All Pixel On mode
Contrast (EV)
Normal
Off
Normal
Off
Normal
Off
Disable
Disable
3Fh
Disable
Disable
3Fh
Disable
Disable
3Fh
Display On/Off
Column: Start Address (XS)
Column: End Address (XE)
Display Off
00h
Display Off
Display Off
00h
83h
00h
83h (when MV=0)
83h
A1h (when MV=1)
Row: Start Address (YS)
Row: End Address (YE)
00h
A1h
00h
A1h
00h
A1h (when MV=0)
83h (when MV=1)
Color set
Random
Random
Contents of the look-up
table protected
Partial: Start Address (PS)
Partial: End Address (PE)
00h
A1h
00h
A1h
00h
A1h
Scroll: Top Fixed Area (TFA)
Scroll: Scroll Area (VSA)
Scroll: Bottom Fixed Area (BFA)
TE On/Off
00h
A2h
00h
00h
A2h
00h
00h
A2h
00h
Off
Off
Off
TE Mode
Memory Data Access Control
MY/MX/MV/ML/RGB)
0 (Mode1)
0 (Mode1)
0 (Mode1)
No Change
00h
00h
Scroll Start Address (SSA)
00h
00h
00h
Idle Mode On/Off
Off
Off
Off
Interface Color Pixel Format (P)
06h (18Bit/Pixel)
TBD
06h (18Bit/Pixel)
TBD
No change
TBD
ID1
ID2
TBD
TBD
TBD
ID3
TBD
TBD
TBD
Drive Duty
A1h
A1h
A1h
First Common
FOSC Divider
Common scan direction
Vop
00h
00h
00h
No division
0→161
142h
No division
0→161
142h
No division
0→161
142h
Ver 1.3
59/208
6/4/2008
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
