ST7669V
7.2 ACCESS TO DDRAM AND INTERNAL REGISTERS
ST7669V realizes high-speed data transfer because the access from MPU is a sort of pipeline processing done via the bus
holder attached to the internal, requiring the cycle time alone without needing the wait time.
For example, when MPU writes data to the DDRAM, the data is once held by the bus holder and then written to the
DDRAM before the succeeding write cycle is started. When MPU reads data from the DDRAM, the first read cycle is
dummy and the bus holder holds the data read in the dummy cycle, and then it read from the bus holder to the system bus
in the succeeding read cycle. Figure 7.2-1 illustrates these relations.
In 80-series interface mode:
MPUꢁsignal
Read
Operation
A0
/WR
/RD
DATA
N
Dummy
D(N)
D(N+1)
Internalꢁsignals
/WR
/RD
INTERNALꢁLATCH
ADDRESSꢁCOUNTER
N
D(N)
D(N+1) D(N+2)
D(N+3)
D(N)
D(N+1) D(N+2)
Figure 7.2-1
Ver 1.3
29/208
6/4/2008
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
