欢迎访问ic37.com |
会员登录 免费注册
发布采购

ST7585 参数 Datasheet PDF下载

ST7585图片预览
型号: ST7585
PDF下载: 下载PDF文件 查看货源
内容描述: 66 ×102点阵LCD控制器/驱动器 [66 x 102 Dot Matrix LCD Controller/Driver]
分类和应用: 驱动器控制器
文件页数/大小: 51 页 / 987 K
品牌: SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
 浏览型号ST7585的Datasheet PDF文件第4页浏览型号ST7585的Datasheet PDF文件第5页浏览型号ST7585的Datasheet PDF文件第6页浏览型号ST7585的Datasheet PDF文件第7页浏览型号ST7585的Datasheet PDF文件第9页浏览型号ST7585的Datasheet PDF文件第10页浏览型号ST7585的Datasheet PDF文件第11页浏览型号ST7585的Datasheet PDF文件第12页  
ST7585
Built-in Power System Pins
Pin Name
V0O
V0I
V0S
XV0O
XV0I
XV0S
VGO
VGI
VGS
BR
I
Power
Power
Power
Type
V0
VG > VM > VSS
XV0
V0O, V0I & V0S should be separated in ITO layout.
V0O, V0I & V0S should be connected together in FPC layout.
LCD driving voltage for commons at positive frame.
XV0O, XV0I & XV0S should be separated in ITO layout.
XV0O, XV0I & XV0S should be connected together in FPC layout.
LCD driving voltage for segments.
VGO, VGI & VGS should be separated in ITO layout.
VGO, VGI & VGS should be connected together in FPC layout.
1.8
VG < VDD2.
Bias circuit configuration pin for default setting :
“L”=1/7; “H”=1/9.
This pin sets the default bias ratio after reset.
Description
LCD driving voltage for commons at negative frame.
No. of Pins
2
4
1
2
4
1
2
4
1
1
Microprocessor Interface Pins
Pin Name
Type
Description
Microprocessor interface select pins.
PS2
“L”
PS[2:0]
I
“L”
“L”
“L”
“H”
PS1
“L”
“L”
“H”
“H”
“L”
PS0
“L”
“H”
“L”
“H”
“L”
Selected Interface
3-Line SPI interface
4-Line SPI interface
6800-series parallel interface
8080-series parallel interface
I C Interface
2
No. of Pins
3
Chip select input pin.
CSB
I
Interface access is enabled when CSB is
“L”.
When CSB is non-active (CSB=“H”), D[7:0] pins are high impedance.
CSB is not used in serial interfaces and should fix to
“H”
by VDD1.
RESB
I
Reset input pin.
When RESB is
“L”,
internal initialization is executed.
It determines whether the access is related to data or command.
A0
I
A0=“H” : Indicates that D[7:0] are display data.
A0=“L” : Indicates that D[7:0] are control data.
A0 is not used in serial interfaces and should fix to
“H”
by VDD1.
Read/Write execution control pin. When parallel interface is selected:
MPU Type
6800 series
RWR
I
8080 series
/WR
RWR
R/W
R/W=“H”: read.
R/W=“L”: write.
Write enable input pin.
Signals on D[7:0] will be latched at the
rising edge of /WR signal.
RWR is not used in serial interfaces and should fix to
“H”
by VDD1.
1
Description
Read/Write control input pin.
1
1
1
Ver 1.0c
8/51
2009/04/14