ST7585
OTP Pins
Pin Name
VPP
Type
Description
No. of Pins
3
Power Programming voltage of OTP.
OTP programming control pin. This pin is pulled high internally.
XEN=”L”, programming OPT is enabled.
XEN
I
1
XEN=”Floating”, programming OPT is disabled.
Test Pins
Pin Name
Type
Test
Test
Test
Description
Do NOT use. Reserved for testing.
No. of Pins
MODE
VMO
TA
1
1
1
Must be “L”. Connect to VSS1 for pull-low.
Output VM for IC testing only.
Do NOT use. Reserved for testing.
Must be “L”. Connect to VSS1 for pull-low.
Recommend ITO Resistance
Pin Name
ITO Resistance
VMO, Reserved
Floating
< 100Ω
< 300Ω
< 1KΩ
VDD1, VDD2, VSS1, VSS2, VPP
V0(V0I, V0O, V0S), VG(VGI, VGO, VGS), XV0(XV0I, XV0O, XV0S), SDA *1
A0, RWR, ERD, CSB, D[7:0] *1
PS[2:0], OSC, BR, TMX, TMY, MODE, TA, XEN
< 5KΩ
RESB *2
< 10KΩ
Note:
1. If using I2C interface mode, the resistance of SDA signal should be lower than 300Ω (if the system pull up resistor is
4.7KΩ).
If using 3-Line or 4-Line SPI interface with VDD1 less than 2.4V, the SDA signal resistance should be less than 500Ω.
2. To prevent the ESD pulse resetting the internal register, applications should increase the resistance of RESB signal
(add a series resistor or increase ITO resistance). The value is different from modules.
3. This table defines the actual ITO resistance. The actual ITO resistance should in these ranges, not the calculated ITO
resistance value. The ITO tolerance should be considered.
4. The option setting to be “H” should connect to VDD1.
5. The option setting to be “L” should connect to VSS1.
Ver 1.0c
10/51
2009/04/14
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
