ST7573
LCD DRIVER CLOCK SUPPLY
When the on-chip oscillator is used, this input must be connected to
V
DD
.
An external clock signal, if used, is connected to this pin. The
OSC
I
oscillator and external clock are both inhibited by connecting the OSC pin
to V
SS
and the display is not clocked and may be left in a DC state. To
avoid this, the chip should always be put into Power Down Mode before
stopping the clock.
POWER SUPPLY PIN
V
SS
Power
Ground.
Digital Supply voltage.
V
DD
Power
The 2 supply rails, V
DD
and V
DD2
, could be connected together (for single
power).
If a Digital Option pin is high, must be this level.
Analog Supply voltage.
V
DD2
VRS
Power
Power
The 2 supply rails, V
DD
and V
DD2
, could be connected together (for single
power).
Reference voltage. Must be left open.
Positive LCD driving voltage for commons.
V0I is the V0 power source for the LCD driver. If using external V0, apply
V0I, V0O, V0S
Power
the external power source on these pads.
V0O is the internal V0 regulator output pad.
V0S is the feedback for the internal V0 voltage compensation circuit.
They should be separate in ITO and be connected together by FPC.
Negative LCD driving voltage for commons.
XV0I is the XV0 power source for the LCD driver. If using external XV0,
XV0I, XV0O,XV0S
Power
apply the external power source on these pads.
XV0O is the internal XV0 regulator output pad.
XV0S is the feedback for the internal XV0 voltage compensation circuit.
They should be separate in ITO and be connected together by FPC.
7
7
1
9
10
3
1
Ver 1.0b
9/46
2007/07/12
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
