ST7573
Read/Write execution control pin (PS[0:1]=[L:H]).
PS2
MPU type
RWR
Description
Read/Write control input pin
R/W=“H”: read;
H
6800-series
R/W
RWR
I
R/W=“L”: write.
1
Write enable clock input pin
The data on D0 to D7 are latched at
the rising edge of the /WR signal.
L
8080-series
/WR
When in the serial interface, left it connected to VDD
.
Read/Write execution control pin (PS[0:1]=[L:H]).
PS2
H
MPU Type
/RD(E)
E
Description
Read/Write control input pin
R/W=“H”: When E is “H”, D0 to D7
are in an output status;
6800-series
R/W=“L”: The data on D0 to D7 are
latched at the falling edge of the E
signal.
ERD
I
1
Read enable clock input pin.
When /RD is “L”, D0 to D7 are in an
output status.
L
8080-series
/RD
When in the serial interface, left it connected to VDD
.
When using 8-bit parallel interface: 6800, 8080
8-bit bi-directional data bus that is connected to the standard 8-bit
microprocessor data bus.
When chip select is not active, D0 to D7 is high impedance.
When using serial interface: 4-LINE
D0: serial input clock (SCLK);
D1, D2, D3: serial input data (SDA), must be connected together;
D4~D7 must be connected to VDD (not used).
When chip select is not active, D0 to D7 is high impedance.
When using serial interface: 3-LINE
D7…D0
I/O
8
D0: serial input clock (SCLK).
D1, D2, D3: serial input data (SDA), must be connected together;
D4~D7 must be connected to VDD (not used).
When chip select is not active, D0 to D7 is high impedance.
Ver 1.0b
8/46
2007/07/12
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
