ST7558
(VDD=1.8V,Ta=-30~85℃)
Rating
Units
Item
Signal
Symbol
tSCYC
Condition
Min.
Max.
—
Serial Clock Period
SCL “H” pulse width
SCL “L” pulse width
Address setup time
Address hold time
Data setup time
Data hold time
200
80
SCL
tSHW
tSLW
tSAS
tSAH
tSDS
tSDH
tCSS
tCSH
—
80
—
60
—
A0
SI
ns
30
—
60
—
30
—
CS-SCL time
40
—
CSB
CS-SCL time
200
—
*1 The input signal rise and fall time (tr, tf) are specified at 15 ns or less.
*2 All timing is specified using 20% and 80% of VDD as the standard.
SERIAL INTERFACE(I2C Interface)
SD A
tBU F
tH IG H
tLO W
SCL
tD H ;STA
tH D ;D A T
tSU ;D A T
(VDD= 1.8V~3.3V,Ta=-30~85℃)
Rating
Units
Item
Signal Symbol
Condition
Min.
Max.
SCL clock frequency
SCL clock low period
SCL clock high period
Data set-up time
SCL FSCLK
SCL TLOW
SCL THIGH
-
200
kHZ
us
us
us
us
ns
ns
pF
us
us
us
ns
us
2.5
2.5
0.1
0
-
-
SI
SI
TSU;Data
THD;Data
-
Data hold time
0.9
SCL,SDA rise time
SCL,SDA fall time
SCL TR
SCL TF
Cb
20+0.1Cb 300
20+0.1Cb 300
Capacitive load represented by each bus line
Setup time for a repeated START condition
Start condition hold time
-
400
SI
SI
TSU;SUA
0.6
0.6
0.6
-
-
THD;STA
TSU;STO
TSW
-
Setup time for STOP ondition
-
Tolerable spike width on bus
50
BUS free time between a STOP and StART condition SCL TBUF
2.5
Ver 2.3
44/56
2005/10/05
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
