ST7558
(VDD = 2.7 V , Ta = -30~85°C )
Rating
Units
Item
Signal
Symbol
tAH8
Condition
Min.
15
Max.
—
Address hold time
A0
Address setup time
tAW8
0
—
System cycle time
tCYC8
tCCLW
tCCHW
tCCLR
tCCHR
tDS8
400
220
180
220
180
40
—
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
—
WR
RD
—
ns
—
—
—
tDH8
0
—
D0 to D7
tACC8
tOH8
CL = 100 pF
CL = 100 pF
—
140
100
READ Output disable time
10
(VDD = 1.8V , Ta = -30~85°C )
Rating
Units
Item
Signal
A0
Symbol
Condition
Min.
30
Max.
—
Address hold time
tAH8
Address setup time
tAW8
0
—
System cycle time
tCYC8
tCCLW
tCCHW
tCCLR
tCCHR
tDS8
640
360
280
360
280
80
—
Enable L pulse width (WRITE)
Enable H pulse width (WRITE)
Enable L pulse width (READ)
Enable H pulse width (READ)
WRITE Data setup time
WRITE Address hold time
READ access time
—
WR
RD
—
—
ns
—
—
tDH8
30
D0 to D7
tACC8
tOH8
CL = 100 pF
CL = 100 pF
—
240
200
READ Output disable time
10
*1 The input signal rise time and fall time (tr, tf) is specified at 15 ns or less. When the system cycle time is extremely fast,
(tr +tf) ≦ (tCYC8 – tCCLW – tCCHW) for (tr + tf) ≦ (tCYC8 – tCCLR – tCCHR) are specified.
*2 All timing is specified using 20% and 80% of VDD as the reference.
*3 tCCLW and tCCLR are specified as the overlap between CSB being “L” and WR and RD being at the “L” level.
Ver 2.3
40/56
2005/10/05
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
