ST7558
Read/Write execution control pin
IMS
MPU type
/WR(R/W)
Description
Read/Write control input pin
R/W=" H “: read
H
6800-series
R/W
R/W=" L”: write
I
2
/WR(R/W)
Write enable clock input pin
The data on D0 to D7 are latched
at the rising edge of the /WR
signal
L
8080-series
/WR
When in the serial interface must fixed to " H ".
Read/Write execution control pin
IMS
H
MPU Type
/RD (E)
E
Description
Read/Write control input pin
R/W=" H “: When E is " H ", D0 to D7
are in an output status.
R/W=" L “: The data on D0 to D7 are
latched at the falling edge of the E
signal.
6800-series
I
2
/RD (E)
Read enable clock input pin
When /RD is " L ", D0 to D7 are in an
output status.
/RD
L
8080-series
When in the serial interface must fixed to " H ".
When the parallel interface selected (P/S=" H " ): 8-bit interface
8-bit bi-directional data bus that is connected to the standard 8-bit
microprocessor data bus.
When chip select is not active, D0 to D7 is high impedance.
When the serial interface selected (P/S=" L " & IMS=”H”):4-line
D7: serial input clock (SCL)
D5 to D0
D6 (SI)
D7 (SCL)
D6: serial input data (SI)
D5, D4, D3, D2, D1, D0: must fix to “H”..
When chip select is not active, D0 to D7 is high impedance.
When the serial interface selected (P/S=" L " & IMS=”L”): I2C
D7: serial clock input (SCL)
D6 , D5 , D4: serial input data (SDA_IN)
D3, D2: (SDA_OUT) serial data acknowledge for the I2C interface. By
connecting SDA_OUT to SDA_IN externally, the SDA line becomes fully
I2C interface compatible. Having the acknowledge output separated
from the serial data line is advantageous in chip on glass (COG)
applications. In COG application where the track resistance from the
SDA_OUT pad to the system SDA line can be significant, a potential
divider is generated by the bus pull-up resistor and the ITO track
resistance. It is possible the during the acknowledge cycle the ST7558
will not be able to create a valid logic 0 level. By splitting the SDA_IN
input from the SDA_OUT output the device could be used in a mode
that ignores the acknowledge bit. In COG applications where the
acknowledge cycle is required, it is necessary to minimize the track
resistance from the SDA_OUT pad to the system SDA line to guarantee
a valid low level.
I/O
16
D0 to D1 (SA)
D2 to D3 (SDA_OUT)
D4 to D6 (SDA_IN)
D7 (SCL)
D6, D5, ….D2 must be connected together (SDA)
D1, D0: Is slave address (SA) bit1, 0, must fix to “H” or “L”
Chip select input pins “CSB” not used must fix to “H”
Ver 2.3
13/56
2005/10/05
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
