ST7066U
l
Interface Timing with External Driver
tct
VOH2
CL1
CL2
D
VOL2
tCWH
tCWH
tCST
tCWL
tct
tDH
tSU
M
tDM
n Power Supply Conditions
Symbol Characteristics
Description
Min. Typ. Max. Unit
Power rise time that will trigger
internal power on reset circuit
The period that I/O is kept low.
tPOR
Power rise time
0.1
100
ms
ms
tIOL
tPW
I/O Low time
40
Enable pulse width
Please refer to the following tables.
1.
2.
During tPOR, VDD noise should be reduced (especially close to 2.0V). Otherwise the
Power-ON-Reset function might be triggered several times and maybe cause unexpected
result.
During tIOL, the I/O ports of the interface (control and data signals) should be kept at “Low”.
V2.2
31/42
2006/05/11
SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
