ST2601B
<LCDCK=32k clock source on ST2602B/ST2608B display>
(1) Control register
Address Name R/W
$047 LCTR
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
R/W
LPWR
BLNK
REV
CAS
GL[3]
GL[2]
GL[1]
GL[0]
1000 0000
Bit 3~2: GL[3:2] : LCD gray-level selection bit
00 = B/W.
01 = 4 gray
10 = 16gray
11 = fast B/W mode
(2)
Address Name
$048 LCKR
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
W
-
-
LMOD[1] LMOD[0] LCK[3] LCK[2] LCK[1] LCK[0]
- - 00 0000
Bit [5:4]: LMOD : LCD data bus mode selection
00 = 1-bit mode
01 = 4-bit mode
1X = 8-bit mode
Bit 3~0: LCKR[3:0] : LCD clock selection (when SYSCK=OSCK)
LCDCK (B/W, 4G, 16G mode)
LCDCK (fast B/W mode)
1-bit mode 4-bit mode 8-bit mode
(LMOD=00) (LMOD=01) (LMOD=1X) (LMOD=00) (LMOD=01) (LMOD=1X)
LCKR[3:0]
1-bit mode
4-bit mode
8-bit mode
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
SYSCK
SYSCK/2
SYSCK/8
SYSCK/16
SYSCK /4
SYSCK /6
SYSCK /8
SYSCK /10
SYSCK /12
SYSCK /14
SYSCK /16
SYSCK /18
SYSCK /20
SYSCK /22
SYSCK /24
SYSCK /26
SYSCK /28
SYSCK /30
SYSCK /32
SYSCK /48
SYSCK /64
SYSCK /80
SYSCK /96
SYSCK /112
SYSCK /128
SYSCK /144
SYSCK /160
SYSCK /176
SYSCK /192
SYSCK /208
SYSCK /224
SYSCK /240
(3) Sysclk is RC:
1. Lcd clock source is Sysclk. If Sysclk is RC, LCD clock source will be RC.
2. In ST2602B, if LCD clock source is RC, B/W, 4G, 16G mode are the same as ST2602.
3. The fast B/W mode is added. In fast B/W mode, the LCDCK will be divided by 8.
4. IF Sysclk is RC and in fast B/W mode, the frame rate is determined as below.
LCDCK
Frame Rate =
LXMAX LFRA +1() ⋅(LYMAX *2)
(4) Sysclk is 32K:
1. If Sysclk is 32k, LCD clock source will be 32k.
2. If Sysclk is 32k, LCD can only display B/W.
3. If LCD clock source is 32k, please set GL[3:2]=11(fash B/W mode) . In this condition, LCKR and LPAN control registers
will avoid. LCDCK is always 32k hz and the frame rate is only controlled by LFRA control register.
4. If LCD clock source is 32k, DC-DC converter clock (LPCK) will also become 32k. So, user must to change LPCK register
to get higher pump frequency(We will provide a macro to take care this part).
5. IF Sysclk is 32K and in fast B/W mode, the frame rate is determined by below equation.
LCDCK
LXMAX LFRA +1() ⋅(LYMAX *2) , where LCDCK is 32K hz.
Frame Rate =
(5) change Sysclk from RC to 32K
Step1: let LCD in fast B/W mode
Step2: use the macro “SWITCH_SYSCLK_RC_TO_32K” to change Sysclk to 32K
(6) change Sysclk from 32K to RC
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SITRONIX [ SITRONIX TECHNOLOGY CO., LTD. ]
