STK15C88
SRAM WRITE CYCLES #1 & #2
(VCC = 5.0V ± 10%)
SYMBOLS
NO.
STK15C88-25
STK15C88-45
PARAMETER
UNITS
#1
#2
Alt.
MIN
25
20
20
10
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
t
t
t
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
20
0
30
0
AVWH
AVEH
AW
t
t
t
AS
AVWL
WHAX
AVEL
EHAX
t
t
t
0
0
WR
h, i
t
t
10
15
WLQZ
WZ
t
t
5
5
WHQX
OW
Note i: If W is low when E goes low, the outputs remain in the high-impedance state.
Note j: E or W must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledj
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
tAVWL
13
tWLWH
W
15
tDVWH
16
tWHDX
DATA IN
DATA VALID
20
tWLQZ
21
tWHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledj
12
tAVAV
ADDRESS
18
tAVEL
14
tELEH
19
tEHAX
E
17
tAVEH
13
tWLEH
W
15
tDVEH
16
tEHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Rev 2.0
Document Control #ML0016
Jan, 2008
5
SIMTEK [ SIMTEK CORPORATION ]
