STK15C88
SRAM READ CYCLES #1 & #2 (VCC = 5.0V ± 10%)
SYMBOLS
STK15C88-25 STK15C88-45
PARAMETER
UNITS
NO.
#1, #2
Alt.
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
AVAVf, t
Read Cycle Time
25
45
f
ELEH
RC
AA
g
3
Address Access Time
25
10
45
20
AVQV
4
Output Enable to Data Valid
GLQV
OE
OH
LZ
g
5
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
5
5
5
5
AXQX
6
ELQX
h
7
10
10
25
15
15
45
EHQZ
HZ
8
0
0
0
0
GLQX
OLZ
OHZ
PA
h
9
GHQZ
e
10
11
ELICCH
,
d
e
Chip Disable to Power Standby
EHICCL
PS
Note f: W must be high during SRAM READ cycles and low during SRAM WRITE cycles.
Note g: I/O state assumes E, G < VIL and W > VIH; device is continuously selected.
Note h: Measured + 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledf, g
2
AVAV
t
ADDRESS
3
t
AVQV
5
t
AXQX
DATA VALID
DQ (DATA OUT)
SRAM READ CYCLE #2: E and G Controlledf
ADDRESS
2
29
tE LE H
tEHAX
1
11
tEHI CC L
tEL Q V
6
E
tELQ X
27
7
tEHQ Z
3
tAV QV
G
9
4
tG L QV
tGH Q Z
8
tG L Q X
DQ (D ATA OUT)
DATA VAL ID
10
tELI CC H
AC TIVE
STAND BY
ICC
Rev 2.0
Document Control #ML0016
Jan, 2008
4
SIMTEK [ SIMTEK CORPORATION ]
