Preliminary
STK14EC8
(program bugs, incoming inspection routines,
etc.).
DATA PROTECTION
The STK14EC8 protects data from corruption during
low-voltage conditions by inhibiting all externally ini-
tiated STORE and WRITE operations. The low-volt-
• The autostore enabled/disabled feature will reset
to “autostore enabled” on every power down
event captured by the nvSRAM. The application
firmware should disable autostore on each reset
sequence that this behavior is desired.
age condition is detected when V <V
.
CC
SWITCH
If the STK14EC8 is in a WRITE mode (both E and
W low) at power-up, after a RECALL, or after a
STORE, the WRITE will be inhibited until a negative
transition on E or W is detected. This protects
against inadvertent writes during power up or brown
out conditions.
• The V
value specified in this datasheet
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
cap
exceed the max V
value because the nvSRAM
cap
internal algorithm calculates V
charge time
cap
NOISE CONSIDERATIONS
The STK14EC8 is a high-speed memory and so
must have a high-frequency bypass capacitor of
based on this max Vcap value. Customers that
want to use a larger V value to make sure
cap
there is extra store charge and store time should
discuss their V size selection with Simtek to
cap
approximately 0.1 µF connected between V
and
CC
understand any impact on the V
voltage level
cap
V
, using leads and traces that are a short as pos-
SS
at the end of a t
period.
RECALL
sible. As with all high-speed CMOS ICs, careful
routing of power, ground, and signals will reduce cir-
cuit noise.
LOW AVERAGE ACTIVE POWER
CMOS technology provides the STK14EC8 with the
benefit of power supply current that scales with
cycle time. Less current will be drawn as the mem-
ory cycle time becomes longer than 50 ns. Figure 4
BEST PRACTICES
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the prod-
uct’s main system values, experience gained work-
ing with hundreds of applications has resulted in the
following suggestions as best practices:
shows the relationship between I
and READ/
CC
WRITE cycle time. Worst-case current consumption
is shown for commercial temperature range,
V
=3.6V, and chip enable at maximum frequency.
CC
• The non-volatile cells in this nvSRAM product are
delivered from Simtek with 0x00 written in all
cells. Incoming inspection routines at customer or
contract manufacturer’s sites will sometimes
reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5,
or 5A. End product’s firmware should not assume
an NV array is in a set programmed state. Rou-
tines that check memory content values to deter-
mine first time system configuration, cold or warm
boot status, etc. should always program a unique
NV pattern (i.e., complex 4-byte pattern of 46 E6
49 53 hex or more random bytes) as part of the
final system manufacturing test to ensure these
system routines work consistently.
Only standby current is drawn when the chip is dis-
abled. The overall average current drawn by the
STK14EC8 depends on the following items:
1
2
3
4
5
6
The duty cycle of chip enable
The overall cycle rate for operations
The ratio of READs to WRITEs
The operating temperature
The VCC Level
I/O Loading
• Power up boot firmware routines should rewrite
the nvSRAM into the desired state (autostore
enabled, etc.). While the nvSRAM is shipped in a
preset state, best practice is to again rewrite the
nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently
Rev 1.1
Document Control #ML0060
Jan, 2008
13
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
