Preliminary
STK14EC8
READ cycles from six specific address locations in
exact order. During the STORE cycle, previous data
is erased and then the new data is programmed into
the nonvolatile elements. Once a STORE cycle is
initiated, further memory inputs and outputs are dis-
abled until the cycle is completed.
To reduce unneeded nonvolatile stores, AutoStore
and Hardware Store operations will be ignored
unless at least one WRITE operation has taken
place since the most recent STORE or RECALL
cycle. Software initiated STORE cycles are per-
formed regardless of whether a WRITE operation
has taken place. The HSB signal can be monitored
by the system to detect an AutoStore cycle is in
progress.
To initiate the software STORE cycle, the following
READ sequence must be performed:
1 Read Address 0x4E38 Valid READ
2 Read Address 0xB1C7 Valid READ
3 Read Address 0x83E0 Valid READ
4 Read Address 0x7C1F Valid READ
5 Read Address 0x703F Valid READ
6 Read Address 0x8FC0 Initiate STORE Cycle
HARDWARE STORE (HSB) OPERATION
The STK14EC8 provides the HSB pin for controlling
and acknowledging the STORE operations. The
HSB pin can be used to request a hardware STORE
cycle. When the HSB pin is driven low, the
STK14EC8 will conditionally initiate a STORE oper-
Once the sixth address in the sequence has been
entered, the STORE cycle will commence and the
chip will be disabled. It is important that READ
cycles and not WRITE cycles be used in the
ation after t
. An actual STORE cycle will only
DELAY
begin if a WRITE to the SRAM took place since the
last STORE or RECALL cycle. The HSB pin has a
very resistive pullup and is internally driven low to
indicate a busy condition while the STORE (initiated
by any means) is in progress. This pin should be
externally pulled up if it is used to drive other inputs.
sequence and that G is active. After the t
cycle
STORE
time has been fulfilled, the SRAM will again be acti-
vated for READ and WRITE operation.
SOFTWARE RECALL
SRAM READ and WRITE operations that are in
Data can be transferred from the nonvolatile mem-
ory to the SRAM by a software address sequence. A
software RECALL cycle is initiated with a sequence
of READ operations in a manner similar to the soft-
ware STORE initiation. To initiate the RECALL cycle,
the following sequence of E controlled or G con-
trolled READ operations must be performed:
progress when HSB is driven low or when V falls
CC
below V
are given time to complete before the
switch
STORE operation is initiated. After AUTOSTORE or
HSB goes low, the STK14EC8 will continue to allow
SRAM operations for t
. During t
, multiple
DELAY
DELAY
SRAM READ operations may take place. If a WRITE
is in progress when HSB is pulled low, it will be
allowed a time, t
SRAM WRITE cycles requested after HSB goes low
will be inhibited until HSB returns high.
, to complete. However, any
DELAY
1 Read Address 0x4E38 Valid READ
2 Read Address 0xB1C7 Valid READ
3 Read Address 0x83E0 Valid READ
4 Read Address 0x7C1F Valid READ
5 Read Address 0x703F Valid READ
6 Read Address 0x4C63 Initiate RECALL Cycle
If HSB is not used, it should be left unconnected.
HARDWARE RECALL (POWER-UP)
During power up or after any low-power condition
(V <V
latched. When V
voltage of V
cally be initiated and will take t
), an internal RECALL request will be
CC
SWITCH
Internally, RECALL is a two-step procedure. First,
the SRAM data is cleared, and second, the nonvola-
tile information is transferred into the SRAM cells.
once again exceeds the sense
CC
, a RECALL cycle will automati-
SWITCH
to complete.
HRECALL
After the t
cycle time, the SRAM will once
RECALL
again be ready for READ or WRITE operations. The
RECALL operation in no way alters the data in the
nonvolatile storage elements. Care must be taken
so the controlling falling edge is glitch and ring free
so as not to double clock the read address.
SOFTWARE STORE
Data can be transferred from the SRAM to the non-
volatile memory by a software address sequence.
The STK14EC8 software STORE cycle is initiated
by executing sequential E controlled or G controlled
Rev 1.1
Document Control #ML0060
Jan, 2008
12
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
