Preliminary
STK14EC16
nvSRAM OPERATION
It is recommended that G be kept high during the
entire WRITE cycle to avoid data bus contention on
common I/O lines. If G is left low, internal circuitry
nvSRAM
The STK14EC16 nvSRAM is made up of two func-
tional components paired in the same physical cell.
These are the SRAM memory cell and a nonvolatile
QuantumTrap cell. The SRAM memory cell operates
like a standard fast static RAM. Data in the SRAM
can be transferred to the nonvolatile cell (the
STORE operation), or from the nonvolatile cell to
SRAM (the RECALL operation). This unique archi-
tecture allows all cells to be stored and recalled in
parallel. During the STORE and RECALL operations
SRAM READ and WRITE operations are inhibited.
The STK14EC16 supports unlimited read and writes
like a typical SRAM. In addition, it provides unlimited
RECALL operations from the nonvolatile cells and
up to 200K STORE operations.
will turn off the output buffers t
low.
after W goes
WLQZ
AutoStore OPERATION
The STK14EC16 stores data to nvSRAM using one
of three storage operations. These three operations
are Hardware Store (activated by HSB), Software
Store (activated by an address sequence), and
AutoStore (on power down).
AutoStore operation is a unique feature of Simtek
Quantum Trap technology that is enabled by default
on the STK14EC16.
During normal operation, the device will draw cur-
rent from V
to charge a capacitor connected to
SRAM READ
The STK14EC16 performs a READ cycle whenever
E and G are low while W and HSB are high. The
address specified on pins A
the 262,144 data words will be accessed. Byte
enables (UB, LB) determine which bytes are
enabled to the output. When the READ is initiated
by an address transition, the outputs will be valid
CC
the V
pin. This stored charge will be used by the
CAP
chip to perform a single STORE operation. If the
voltage on the V pin drops below V , the
part will automatically disconnect the V
CC
SWITCH
determine which of
0-17
pin from
CAP
V
. A STORE operation will be initiated with power
CC
provided by the V
capacitor.
CAP
Figure 3 shows the proper connection of the storage
capacitor (V ) for automatic store operation.
after a delay of t
(READ cycle #1). If the READ
AVQV
CAP
is initiated by E and G, the outputs will be valid at
or at t , whichever is later (READ cycle
Refer to the DC CHARACTERISTICS table for the
size of the capacitor. The voltage on the V pin is
t
ELQV
GLQV
CAP
#2). The data outputs will repeatedly respond to
address changes within the t access time with-
out the need for transitions on any control input pins,
and will remain valid until another address change
or until E or G is brought high, or W and HSB is
brought low.
driven to 3.6V by a regulator on the chip. A pull up
should be placed on W to hold it inactive during
power up.This pull-up is only effective if the W signal
AVQV
SRAM WRITE
vCC
A WRITE cycle is performed whenever E and W are
low and HSB is high. The address inputs must be
stable prior to entering the WRITE cycle and must
remain stable until either E or W goes high at the
end of the cycle. The data on the common I/O pins
DQ0-15 will be written into memory if it is valid
vCC
vCAP
W
t
t
before the end of a W controlled WRITE or
before the end of an E controlled WRITE. The
DVWH
DVEH
Byte Enable inputs (UB, LB) determine which bytes
are written.
Figure 3. AutoStore Mode
Rev 1.1
Document Control #ML0061
Jan, 2008
12
Simtek Confidential
SIMTEK [ SIMTEK CORPORATION ]
