STK14CC8
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
STK14CC8-25 UNITS
PARAMETER
#1
#2
Alt.
tWC
tWP
tCW
tDW
tDH
MIN
25
20
20
10
0
MAX
Write Cycle Time
12
13
14
15
16
17
18
19
20
21
tAVAV
tWLWH
tELWH
tDVWH
tWHDX
tAVWH
tAVWL
tWHAX
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
tAW
tAS
20
0
tWR
tWZ
tOW
0
e,g
tWLQZ
10
tWHQX
3
Notes
g: If
h:
W
is low when E goes low, the outputs remain in the high-impedance state.
E
or
W
must be ≥ VIH during address transitions.
SRAM WRITE CYCLE #1: W Controlledh,f
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
13
tWLWH
tAVWL
W
15
16
tDVWH
tWHDX
DATA VALID
DATA IN
20
tWLQZ
21
tWHQX
HIGH IMPEDANCE
PREVIOUS DATA
DATA OUT
SRAM WRITE CYCLE #2: E Controlledh,f
12
tAVAV
ADDRESS
September 2005
6
Document Control #ML0034 rev 0.0
SIMTEK [ SIMTEK CORPORATION ]
