STK14CA8
SRAM WRITE CYCLES #1 & #2
SYMBOLS
NO.
STK14CA8-25
STK14CA8-35
STK14CA8-45
PARAMETER
UNITS
#1
#2
Alt.
tWC
tWP
tCW
tDW
tDH
tAW
tAS
MIN
25
20
20
10
0
MAX
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
12
13
14
15
16
17
18
19
20
21
tAVAV
tAVAV
tWLEH
tELEH
tDVEH
tEHDX
tAVEH
tAVEL
tEHAX
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tWLWH
tELWH
tDVWH
tWHDX
tAVWH
tAVWL
tWHAX
Write Pulse Width
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
20
0
25
0
30
0
tWR
tWZ
tOW
0
0
0
e, g
tWLQZ
10
13
15
tWHQX
3
3
3
Note g: If W is low when E goes low, the outputs remain in the high-impedance state.
Note h: E or W must be ≥ VIH during address transitions.
g,h
SRAM WRITE CYCLE #1: W Controlled
12
tAVAV
ADDRESS
19
tWHAX
14
tELWH
E
17
tAVWH
18
tAVWL
13
tWLWH
W
DATA IN
15
tDVWH
16
tWHDX
DATA VALID
20
tWLQZ
21
tWHQX
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
g,h
SRAM WRITE CYCLE #2: E Controlled
12
tAVAV
ADDRESS
18
tAVEL
14
tELEH
19
tEHAX
E
17
tAVEH
13
tWLEH
W
15
tDVEH
16
tEHDX
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
Rev 2.1
Document Control #ML0022
Jan, 2008
6
SIMTEK [ SIMTEK CORPORATION ]
