STK14C88
SRAM READ CYCLES #1 & #2
(VCC = 5.0V ± 10%)e
SYMBOLS
STK14C88-25
STK14C88-35
STK14C88-45
NO.
PARAMETER
UNITS
#1, #2
Alt.
MIN
MAX
MIN
MAX
MIN
MAX
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ELQV
ACS
RC
AA
g
g
t
ELEH
Read Cycle Time
25
35
45
AVAV
,
h
3
Address Access Time
25
10
35
15
45
20
AVQV
4
Output Enable to Data Valid
GLQV
AXQX
ELQX
EHQZ
GLQX
OE
OH
LZ
h
5
Output Hold after Address Change
Address Change or Chip Enable to Output Active
Address Change or Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
5
5
5
5
5
5
6
i
7
10
10
25
13
13
35
15
15
45
HZ
8
0
0
0
0
0
0
OLZ
OHZ
PA
i
9
GHQZ
f
f
10
11
ELICCH
EHICCL
Chip Disable to Power Standby
PS
Note g: W and HSB must be high during SRAM READ cycles.
Note h: I/O state assumes E and G < V and W > V ; device is continuously selected.
IL
IH
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
2
AVAV
t
ADDRESS
3
AVQV
t
5
AXQX
t
DQ (DATA OUT)
DATA VALID
SRAM READ CYCLE #2: E and G Controlledg
ADDRESS
2
29
tE LE H
tEHAX
1
11
tEHI CC L
tEL Q V
6
E
tELQ X
27
7
tEHQ Z
3
tAV QV
G
9
4
tG L QV
tGH Q Z
8
tG L Q X
DQ (D ATA OUT)
DATA VAL ID
10
tELI CC H
AC TIVE
STAND BY
ICC
Rev 2.0
Document Control #ML0014
Feb, 2008
4
SIMTEK [ SIMTEK CORPORATION ]
