STK14C88
PIN CONFIGURATIONS
VCAP
1
VCC
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A14
2
HSB
3
A12
A7
W
A13
A8
A9
4
A13
A8
A6
A5
A4
A3
A6
A5
A4
A3
5
6
A9
A11
7
A11
G
(TOP)
(TOP)
8
G
NC
A2
NC
A10
NC
A2
NC
9
A1
10
11
12
13
14
15
16
A10
A0
E
A1
A0
E
DQ0
DQ7
DQ7
DQ0
DQ1
DQ2
VSS
DQ6
DQ5
DQ4
DQ3
32-Pin 450 mil LCC
32-Pin 300 mil SOIC
32-Pin 300 mil CDIP
PIN DESCRIPTIONS
Pin Name
I/O
Description
A
-A
Input
I/O
Address: The 15 address inputs select one of 32,768 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
14
0
DQ -DQ
7
0
E
Input
Input
W
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
G
Input
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
V
Power Supply
I/O
Power: 5.0V, +10%
CC
HSB
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
V
V
Power Supply
Power Supply
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
CAP
SS
Ground
Rev 2.0
Document Control #ML0014
Feb, 2008
2
SIMTEK [ SIMTEK CORPORATION ]
