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STK14C88-3WF45 参数 Datasheet PDF下载

STK14C88-3WF45图片预览
型号: STK14C88-3WF45
PDF下载: 下载PDF文件 查看货源
内容描述: 32Kx8自动存储的nvSRAM [32Kx8 AutoStore nvSRAM]
分类和应用: 存储内存集成电路静态存储器光电二极管
文件页数/大小: 17 页 / 495 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
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STK14C88-3  
e
SRAM READ CYCLES #1 & #2  
(V = 3V - 3.6V)  
CC  
SYMBOLS  
NO.  
STK14C88-3-35 STK14C88-3-45  
PARAMETER  
UNITS  
#1, #2  
Alt.  
MIN  
MAX  
MIN  
MAX  
1
2
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time  
35  
45  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ELQV  
ACS  
RC  
AA  
g
Read Cycle Time  
35  
45  
AVAV  
h
3
Address Access Time  
35  
15  
45  
20  
AVQV  
4
Output Enable to Data Valid  
Output Hold after Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
GLQV  
OE  
OH  
LZ  
h
5
5
5
5
5
AXQX  
6
ELQX  
i
7
13  
13  
35  
15  
15  
45  
EHQZ  
HZ  
8
0
0
0
0
GLQX  
OLZ  
OHZ  
PA  
i
9
GHQZ  
f
f
10  
11  
ELICCH  
EHICCL  
PS  
Note g: W and HSB must be high during SRAM READ cycles and low during SRAM WRITE cycles.  
Note h: /O state assumes E and G < V and W > V ; device is continuously selected.  
IL  
IH  
Note i: Measured 200mV from steady state output voltage.  
g, h  
SRAM READ CYCLE #1: Address Controlled  
2
AVAV  
t
ADDRESS  
3
AVQV  
t
5
AXQX  
t
DQ (DATA OUT)  
DATA VALID  
g
SRAM READ CYCLE #2: E Controlled  
2
AVAV  
t
ADDRESS  
E
1
ELQV  
11  
EHICCL  
t
t
6
ELQX  
t
7
EHQZ  
t
G
9
4
GLQV  
t
GHQZ  
t
8
GLQX  
t
DATA VALID  
DQ (DATA OUT)  
10  
ELICCH  
t
ACTIVE  
STANDBY  
I
CC  
Rev 0.6  
Document Control #ML0015  
February 2007  
5