STK14C88-3
SRAM WRITE CYCLES #1 & #2
(VCC = 3.0V-3.6V)e
SYMBOLS
STK14C88-3-35 STK14C88-3-45
STK14C88-3-55
NO.
PARAMETER
UNITS
#1
#2
Alt.
MIN
35
25
25
12
0
MAX
MIN
45
30
30
15
0
MAX
MIN
55
40
40
25
0
MAX
12
13
14
15
16
17
18
19
20
21
t
t
t
WC
Write Cycle Time
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVAV
AVAV
t
t
t
Write Pulse Width
WLWH
WLEH
WP
CW
DW
t
t
t
t
Chip Enable to End of Write
Data Set-up to End of Write
Data Hold after End of Write
Address Set-up to End of Write
Address Set-up to Start of Write
Address Hold after End of Write
Write Enable to Output Disable
Output Active after End of Write
ELWH
DVWH
WHDX
ELEH
DVEH
EHDX
t
t
t
t
t
DH
AW
t
t
t
25
0
30
0
40
0
AVWH
AVEH
t
t
t
AVWL
WHAX
AVEL
EHAX
AS
t
t
t
0
0
0
WR
i, j
t
t
13
15
20
WLQZ
WZ
t
t
5
5
5
WHQX
OW
Note j: If W is low when E goes low, the outputs remain in the high-impedance state.
Note k: E or W must be ≥ VIH during address transitions.
Note l: HSB must be high during SRAM WRITE cycles.
SRAM WRITE CYCLE #1: W Controlledk, l
12
AVAV
t
ADDRESS
19
WHAX
14
ELWH
t
t
E
17
AVWH
t
18
AVWL
t
13
WLWH
t
W
15
16
WHDX
t
t
DVWH
DATA VALID
DATA IN
DATA IN
20
WLQZ
t
21
WHQX
t
HIGH IMPEDANCE
DATA OUT
PREVIOUS DATA
SRAM WRITE CYCLE #2: E Controlledk, l
12
AVAV
t
ADDRESS
18
AVEL
14
ELEH
19
t
t
t
EHAX
E
17
AVEH
t
13
WLEH
t
W
15
DVEH
16
EHDX
t
t
DATA IN
DATA VALID
HIGH IMPEDANCE
DATA OUT
November 2003
4
Document Control # ML0015 rev 0.3
SIMTEK [ SIMTEK CORPORATION ]
