STK12C68, STK12C68-5 (SMD5962-94599)
100
80
100
80
60
60
TTL
40
20
40
20
CMOS
TTL
CMOS
0
0
50
100
150
200
50
100
150
200
Cycle Time (ns)
Cycle Time (ns)
Figure 4: Icc (max) Reads
Figure 5: Icc (max) Writes
desired state as a safeguard against events that
might flip the bit inadvertently (program bugs,
incoming inspection routines, etc.).
BEST PRACTICES
nvSRAM products have been used effectively for
over 15 years. While ease-of-use is one of the
product’s main system values, experience gained
working with hundreds of applications has resulted
in the following suggestions as best practices:
• The Vcap value specified in this datasheet
includes a minimum and a maximum value size.
Best practice is to meet this requirement and not
exceed the max Vcap value because the higher
inrush currents may reduce the reliability of the
internal pass transistor. Customers that want to
use a larger Vcap value to make sure there is
extra store charge should discuss their Vcap size
selection with Simtek.
• The non-volatile cells in an nvSRAM are pro-
grammed on the test floor during final test and
quality assurance. Incoming inspection routines
at customer or contract manufacturer’s sites will
sometimes reprogram these values. Final NV
patterns are typically repeating patterns of AA,
55, 00, FF, A5, or 5A. End product’s firmware
should not assume an NV array is in a set pro-
grammed state. Routines that check memory
content values to determine first time system
configuration, cold or warm boot status, etc.
should always program a unique NV pattern
(e.g., complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final sys-
tem manufacturing test to ensure these system
routines work consistently.
• Power up boot firmware routines should rewrite
the nvSRAM into the desired state. While the
nvSRAM is shipped in a preset state, best prac-
tice is to again rewrite the nvSRAM into the
Rev 2.0
Document Control #ML0008
June, 2008
12