欢迎访问ic37.com |
会员登录 免费注册
发布采购

SMD5962-9459903MXX 参数 Datasheet PDF下载

SMD5962-9459903MXX图片预览
型号: SMD5962-9459903MXX
PDF下载: 下载PDF文件 查看货源
内容描述: [Non-Volatile SRAM, 8KX8, 35ns, CMOS, CDIP28, 0.300 INCH, CERAMIC, DIP-28]
分类和应用: 静态存储器内存集成电路
文件页数/大小: 21 页 / 834 K
品牌: SIMTEK [ SIMTEK CORPORATION ]
 浏览型号SMD5962-9459903MXX的Datasheet PDF文件第7页浏览型号SMD5962-9459903MXX的Datasheet PDF文件第8页浏览型号SMD5962-9459903MXX的Datasheet PDF文件第9页浏览型号SMD5962-9459903MXX的Datasheet PDF文件第10页浏览型号SMD5962-9459903MXX的Datasheet PDF文件第12页浏览型号SMD5962-9459903MXX的Datasheet PDF文件第13页浏览型号SMD5962-9459903MXX的Datasheet PDF文件第14页浏览型号SMD5962-9459903MXX的Datasheet PDF文件第15页  
STK12C68, STK12C68-5 (SMD5962-94599)  
If HSB is not used, it should be left unconnected.  
HSB OPERATION  
The STK12C68, STK12C68-5 provides the HSB pin  
for controlling and acknowledging the STORE opera-  
tions. The HSB pin is used to request a hardware  
STORE cycle. When the HSB pin is driven low, the  
STK12C68, STK12C68-5 will conditionally initiate a  
STORE operation after tDELAY; an actual STORE cycle  
will only begin if a WRITE to the SRAM took place  
since the last STORE or RECALL cycle. The HSB pin  
has a very resistive pullup and is internally driven  
low to indicate a busy condition while the STORE  
(initiated by any means) is in progress.  
PREVENTING STORES  
The STORE function can be disabled on the fly by  
holding HSB high with a driver capable of sourcing  
30mA at a VOH of at least 2.2V, as it will have to  
overpower the internal pull-down device that drives  
HSB low for 20μs at the onset of a STORE. When  
the STK12C68, STK12C68-5 is connected for  
AutoStore operation (system VCC connected to VCC  
and a 68μF capacitor on VCAP) and VCC crosses  
VSWITCH on the way down, the STK12C68,  
STK12C68-5 will attempt to pull HSB low; if HSB  
doesn’t actually get below VIL, the part will stop try-  
ing to pull HSB low and abort the STORE attempt.  
SRAM READ and WRITE operations that are in  
progress when HSB is driven low by any means are  
given time to complete before the STORE operation  
is initiated. After HSB goes low, the STK12C68,  
STK12C68-5 will continue SRAM operations for tDE-  
HARDWARE PROTECT  
The STK12C68, STK12C68-5 offers hardware pro-  
tection against inadvertent STORE operation and  
SRAM WRITEs during low-voltage conditions. When  
VCAP < VSWITCH, all externally initiated STORE opera-  
tions and SRAM WRITEs are inhibited.  
. During tDELAY, multiple SRAM READ operations  
LAY  
may take place. If a WRITE is in progress when HSB  
is pulled low it will be allowed a time, tDELAY, to com-  
plete. However, any SRAM WRITE cycles requested  
after HSB goes low will be inhibited until HSB  
returns high.  
AutoStore can be completely disabled by tying VCC  
to ground and applying + 5V to VCAP. This is the  
AutoStore Inhibit mode; in this mode, STOREs are  
only initiated by explicit request using either the soft-  
ware sequence or the HSB pin.  
The HSB pin can be used to synchronize multiple  
STK12C68, STK12C68-5s while using a single  
larger capacitor. To operate in this mode the HSB  
pin should be connected together to the HSB pins  
from the other STK12C68, STK12C68-5s. An exter-  
nal pull-up resistor to + 5V is required since HSB  
acts as an open drain pull down. The VCAP pins from  
the other STK12C68, STK12C68-5 parts can be tied  
together and share a single capacitor. The capacitor  
size must be scaled by the number of devices con-  
nected to it. When any one of the STK12C68,  
STK12C68-5s detects a power loss and asserts  
HSB, the common HSB pin will cause all parts to  
request a STORE cycle (a STORE will take place in  
those STK12C68, STK12C68-5s that have been  
written since the last nonvolatile cycle).  
LOW AVERAGE ACTIVE POWER  
The STK12C68, STK12C68-5 draws significantly  
less current when it is cycled at times longer than  
50ns. Figure 4 shows the relationship between ICC  
and READ cycle time. Worst-case current consump-  
tion is shown for both CMOS and TTL input levels  
(commercial temperature range, VCC = 5.5V, 100%  
duty cycle on chip enable). Figure 5 shows the  
same relationship for WRITE cycles. If the chip  
enable duty cycle is less than 100%, only standby  
current is drawn when the chip is disabled. The  
overall average current drawn by the STK12C68,  
STK12C68-5 depends on the following items: 1)  
CMOS vs. TTL input levels; 2) the duty cycle of chip  
enable; 3) the overall cycle rate for accesses; 4) the  
ratio of READs to WRITEs; 5) the operating tempera-  
ture; 6) the Vcc level; and 7) I/O loading.  
During any STORE operation, regardless of how it  
was initiated, the STK12C68, STK12C68-5 will con-  
tinue to drive the HSB pin low, releasing it only when  
the STORE is complete. Upon completion of the  
STORE operation the STK12C68, STK12C68-5 will  
remain disabled until the HSB pin returns high.  
Rev 2.0  
Document Control #ML0008  
June, 2008  
11  
 复制成功!