SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
Register Definitions
This section describes the registers within the SiI3114.
PCI Configuration Space
The PCI Configuration Space registers define he operation of the SiI3114 on the PCI bus. These registers are
accessible only when the SiI3114 detects a Configuration Read or Write operation, with its IDSEL asserted, on
the 32-bit PCI bus. Table 16 outlines the PCI Configuration space for the SiI3114.
Table 16. SiI3114 PCI Configuration Space
Address
Offset
Register Name
16 15
Access
Type
31
00
00H
04H
08H
0CH
10H
14H
18H
1CH
20H
24H
28H
2CH
30H
34H
38H
3CH
40H
44H
48H
4CH
50H
54H
58H
5CH
60H
64H
68H
6CH
70H
Device ID
Vendor ID
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
-
PCI Status
PCI Command
PCI Class Code
Header Type
Revision ID
Cache Line Size
BIST
Latency Timer
Base Address Register 0
Base Address Register 1
Base Address Register 2
Base Address Register 3
Base Address Register 4
Base Address Register 5
Reserved
Subsystem ID
Subsystem Vendor ID
R/W
R/W
R
Expansion ROM Base Address
Reserved
Capabilities Ptr
Reserved
R/W
R/W
R/W
R/W
-
Max Latency
Reserved
Min Grant
Interrupt Pin
Interrupt Line
Configuration
Software Data Register
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
Power Management Capabilities
Next Item Pointer
Capability ID
R/W
R/W
-
Data
Reserved
Functions Control and Status
Reserved
Reserved
-
Reserved
PCI Bus Master
Status – Channel
0/2
Reserved
PCI Bus Master
Command –
Channel 0/2
R/W
74H
78H
PRD Table Address – Channel 0/2
R/W
R/W
Reserved
PCI Bus Master
Status – Channel
1/3
Reserved
PCI Bus Master
Command –
Channel 1/3
7CH
80H
PRD Table Address – Channel 1/3
Reserved
R/W
R/W
Channel 0/2 Data
Transfer Mode
© 2007 Silicon Image, Inc.
25
SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
