SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
PCI 66 MHz Timing Specifications
Table 8. PCI 66 MHz Timing Specifications
Symbol Parameter
Limits
Unit
Min
2.0
2.0
2.0
-
Max
TVAL
CLK to Signal Valid – Bussed Signals
6.0
ns
ns
ns
ns
ns
ns
ns
TVAL (PTP) CLK to Signal Valid – Point to Point
6.0
TON
TOFF
TSU
Float to Active Delay
-
Active to Float Delay
14.0
Input Setup Time – Bussed Signals
Input Setup Time – Point to Point
Input Hold Time
3.0
5.0
0.0
-
-
-
TSU (PTP)
TH
Flash Memory Timing Specifications
PCICLK
FL_ADDR
FL_CS_N
FL_RD_N
2 TCYC
15 TCYC
1 TCYC
FLASH READ TIMING
PCICLK
FL_ADDR
FL_CS_N
FL_WR_N
2 TCYC
15 TCYC
13 TCYC
FLASH WRITE TIMING
Figure 2. Flash Memory Timing
© 2007 Silicon Image, Inc.
7
SiI-DS-0103-D
SILICONIMAGE [ Silicon image ]
