SiI3114 PCI to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
SATA Interface Transmitter Output Jitter Characteristics
Table 5. SATA Interface Transmitter Output Jitter Characteristics
Symbol Parameter
Condition
Limits
Typ
Unit
Min
Max
RJ5UI
RJ250UI
DJ5UI
5UI later Random Jitter
Measured at Tx output pins
1sigma deviation
-
4.5
-
-
-
ps rms
ps rms
ps
250UI later Random
Jitter
Measured at Tx output pins
1sigma deviation
-
-
6.0
40
5UI later Deterministic
Jitter
Measured at Tx output pins peak
to peak phase variation Random
data pattern
DJ250UI
250UI later Deterministic Measured at Tx output pins peak
-
45
-
ps
Jitter
to peak phase variation Random
data pattern
CLKI SerDes Reference Clock Input Requirements
Table 6. CLKI SerDes Reference Clock Input Requirements
Symbol
Parameter
Condition
Limits
Typ
Unit
Min
Max
TCLKI_FREQ
Nominal Frequency
Input High Voltage
REXT = 1k 1%
REXT = 4.99k 1%
-
25
100
-
MHz
V
VCLK_IH
VCLK_IL
TCLKI_J
-
0.7xVDDX
-
-
-
Input Low Voltage
-
-
-
-100
-
0.3xVDDX
+100
V
ppm
ns
CLKI frequency tolerance
TCLKI_RISE_FALL Rise and Fall time at CLKI 25MHz reference clock,
-
4
2
20%-80%
100MHz reference clock,
20%-80%
TCLKI_RC_DUTY CLKI duty cycle
20%-80%
40
-
60
%
Notes: CLKI must be 1.8V swing when external clock input to this pin
PCI 33 MHz Timing Specifications
Table 7. PCI 33 MHz Timing Specifications
Symbol
Parameter
Limits
Unit
Min
2.0
2.0
2.0
-
Max
TVAL
CLK to Signal Valid – Bussed Signals
11.0
ns
ns
ns
ns
ns
ns
ns
TVAL (PTP) CLK to Signal Valid – Point to Point
11.0
TON
TOFF
TSU
Float to Active Delay
-
Active to Float Delay
28.0
Input Setup Time – Bussed Signals
Input Setup Time – Point to Point
Input Hold Time
7.0
10.0
0.0
-
-
-
TSU (PTP)
TH
SiI-DS-0103-D
6
© 2007 Silicon Image, Inc.
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