S i 5 3 5 / 5 36
R
EVISION
D
U
L T R A
L
O W
J
ITTER
C
RYSTAL
O
SCILLATOR
(XO)
Features
Available with select frequencies from
Available with LVPECL and
100 MHz to 312.5 MHz
LVDS outputs
3rd generation DSPLL
®
with superior
3.3 and 2.5 V supply options
Industry-standard 5 x 7 mm
jitter performance and high-power
package and pinout
supply noise rejection
Pb-free/RoHS-compliant
3x better frequency stability than
SAW-based oscillators
Si5602
Applications
Ordering Information:
See page 7.
10/40/100G data centers
10G Ethernet switches/routers
Fibre channel/SAS/storage
Enterprise servers
Networking
Telecommunications
Description
The Si535/536 XO utilizes Silicon Laboratories’ advanced DSPLL
®
circuitry
to provide an ultra low jitter clock at high-speed differential frequencies.
Unlike a traditional XO, where a different crystal is required for each output
frequency, the Si535/536 uses one fixed crystal to provide a wide range of
output frequencies. This IC based approach allows the crystal resonator to
provide exceptional frequency stability and reliability. In addition, DSPLL
clock synthesis provides superior supply noise rejection, simplifying the task
of generating low jitter clocks in noisy environments typically found in
communication systems. The Si535/536 IC based XO is factory programmed
at time of shipment, thereby eliminating long lead times associated with
custom oscillators.
Pin Assignments:
See page 6.
(Top View)
NC
1
6
V
DD
OE
2
5
CLK–
GND
3
4
CLK+
Si535
Functional Block Diagram
V
DD
CLK– CLK+
OE
1
6
V
DD
NC
2
5
CLK–
GND
3
4
CLK+
Si536
Fixed
Frequency
XO
100–312.5 MHz
DSPLL
®
Clock Synthesis
OE
GND
Preliminary Rev. 0.6 7/13
Copyright © 2013 by Silicon Laboratories
Si535/536
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
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