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SI3225-FQ 参数 Datasheet PDF下载

SI3225-FQ图片预览
型号: SI3225-FQ
PDF下载: 下载PDF文件 查看货源
内容描述: 双PROSLIC®可编程CMOS SLIC / CODEC [DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC]
分类和应用: 电池电信集成电路
文件页数/大小: 108 页 / 1519 K
品牌: SILICONIMAGE [ Silicon image ]
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Si3220/Si3225  
Tone Generator Interrupts  
requirements.  
Both the active and inactive timers can generate an The register and RAM locations for caller ID generation  
interrupt to signal “on/off” transitions to the software. are listed in Table 36. Caller ID data is entered into the  
The timer interrupts for tone generator 1 can be 8-bit FSKDAT register. The data byte is double buffered  
individually enabled by setting the OS1TAE and OS1TIE so that the Dual ProSLIC can generate an interrupt  
bits. Timer interrupts for tone generator 2 are OS2TAE indicating the next data byte can be written when  
and OS2TIE. A pending interrupt for each of the timers processing begins on the current data byte. The caller  
is determined by reading the OS1TAS, OS1TIS, ID data can be transmitted in one of two modes  
OS2TAS, and OS2TIS bits in the IRQVEC1 register.  
Caller ID Generation  
controlled by the O1FSK8 register bit. When  
O1FSK8 = 0 (default case), the 8-bit caller ID data is  
transmitted with a start bit and stop bit to create a 10-bit  
data sequence. If O1FSK8 = 1, the caller ID data is  
transmitted as a raw 8-bit sequence with no start or stop  
bits. The value programmed into the OSC1TA register  
determines the bit rate, and the interrupt rate is equal to  
the bit rate divided by the data sequence length (8 or 10  
bits).  
The Dual ProSLIC devices generate caller ID signals in  
compliance with various Bellcore and ITU specifications  
as described in Table 35 by providing continuous phase  
binary frequency shift keying (FSK) modulation.  
Oscillator 1 is required because it preserves phase  
continuity during frequency shifts whereas Oscillator 2  
does not. Figure 37 illustrates a typical caller ID  
transmission sequence in accordance with Bellcore  
Table 35. FSK Modulation Requirements  
Parameter  
ITU-T V.23  
1300 Hz  
2100 Hz  
Bellcore GR-30-CORE  
1200 Hz  
2200 Hz  
1200 baud  
Mark Frequency (logic 1)  
Space Frequency (logic 0)  
Transmission Rate  
Table 36. Register and RAM Locations used for Caller ID Generation  
Parameter  
Register/RAM Register/RAM Bits  
Mnemonic  
Description/Range  
(LSB Size)  
Enable/disable  
0 to 2.73 s (41.66 µs)*  
Caller ID data  
FSK Start & Stop Bit Enable  
Oscillator 1 Active Timer  
FSK Data Byte  
OMODE  
O1TALO/O1TAHI  
FSKDAT  
O1FSK8  
OSC1TA[15:0]  
FSKDAT[7:0]  
FSK Frequency for Space  
FSK Frequency for Mark  
FSK Amplitude for Space  
FSK Amplitude for Mark  
FSK 0-1 Transition Freq, High  
FSK 0-1 Transition Freq, Low  
FSK 1-0 Transition Freq, High  
FSK 1-0 Transition Freq, Low  
FSKFREQ0  
FSKFREQ1  
FSKAMP0  
FSKAMP1  
FSK01HI  
FSKFREQ0[15:3]  
FSKFREQ1[15:3]  
FSKAMP0[15:3]  
FSKAMP1[15:3]  
FSK01HI[15:3]  
FSK01LO[15:3]  
FSK10HI[15:3]  
FSK10LO[15:3]  
Audio range  
Audio range  
FSK01LO  
FSK10HI  
FSK10LO  
*Note: Oscillator 1 active timer range and LSB stage valid only for FSK mode.  
Rev. 1.0  
63  
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