Si3220/Si3225
the appropriate coefficients for the FIR and IIR filter architecture. The register set for tone generation is
blocks.
summarized in Table 34.
The transhybrid balance filters can be disabled to
implement loopback diagnostic modes. To disable the
transhybrid balance filter (zero cancellation), set the
HYBDIS bit in the DIGCON register to 1.
Note: The user must enter values into each register location
to ensure correct operation when the hybrid balance
block is enabled.
Oscillator Frequency and Amplitude
Each of the two tone generators contains a two-pole
resonant oscillator circuit with
a
programmable
frequency and amplitude, which are programmed via
RAM addresses OSC1FREQ, OSC1AMP, OSC1PHAS,
OSC2FREQ, OSC2AMP, and OSC2PHAS. The sample
rate for the two oscillators is 8000 Hz. The equations
are as follows:
Tone Generators
coeff = cos(2π f /8000 Hz),
n
n
Dual ProSLIC devices have two digital tone generators
that allow a wide variety of single or dual tone frequency
and amplitude combinations that spare the user the
effort of generating the required POTS signaling tones
on the PCM highway. DTMF, FSK (caller ID), call
progress, and other tones can all be generated on-chip.
The tones are sent to the receive or transmit paths.
(See Figure 11 on page 24.)
where f is the frequency to be generated;
n
14
OSCnFREQ = coeff x (2 );
n
1
15
Desired Vrms
1 – coeff
--
---------------------------------------
OSCnAMP =
----------------------- × (2 – 1) ×
1 + coeff
4
1.11 Vrms
where Desired Vrms is the amplitude to be generated;
OSCnPHAS = 0,
n = 1 or 2 for oscillator 1 or oscillator 2, respectively.
For example, to generate a DTMF digit of 8, the two
required tones are 852 Hz and 1336 Hz. Assuming we
want to generate half-scale values (ignoring twist), the
following values are calculated:
Tone Generator Architecture
A simplified diagram of the tone generator architecture
is shown in Figure 35. The oscillator, active/inactive
timers, interrupt block, and signal routing block are
connected for flexibility in creating audio signals.
Control and status register bits are placed in the figure
to indicate their association with the tone generator
8 kHz
Clock
8 kHz
Clock
ZEROENn
Zero Cross
OSCnEN
ENSYNCn
to TX Path
Enable
Zero
Cross
Logic
16-Bit
Modulo
Counter
Two-Pole
OSCnTA
Expire
Signal
Resonant
Routing
Register
Load
Oscillator
OSCnTI
Expire
Load
Logic
to RX Path
OSCnTA
OSCnFREQ
REL*
INT
OSCnTAEN
OSnTIS
Logic
ROUTn
OSCnTI
OSCnAMP
OSnTIE
OSnTAS
INT
OSCnTIEN
Logic
OSCnPHAS
OSnTAE
*Tone Generator 1 Only
n = "1" or "2" for Tone Generator 1 and 2, respectively
Figure 35. Tone Generator Diagram
Rev. 1.0
59
SILICONIMAGE [ Silicon image ]
