欢迎访问ic37.com |
会员登录 免费注册
发布采购

SI3225-FQ 参数 Datasheet PDF下载

SI3225-FQ图片预览
型号: SI3225-FQ
PDF下载: 下载PDF文件 查看货源
内容描述: 双PROSLIC®可编程CMOS SLIC / CODEC [DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC]
分类和应用: 电池电信集成电路
文件页数/大小: 108 页 / 1519 K
品牌: SILICONIMAGE [ Silicon image ]
 浏览型号SI3225-FQ的Datasheet PDF文件第42页浏览型号SI3225-FQ的Datasheet PDF文件第43页浏览型号SI3225-FQ的Datasheet PDF文件第44页浏览型号SI3225-FQ的Datasheet PDF文件第45页浏览型号SI3225-FQ的Datasheet PDF文件第47页浏览型号SI3225-FQ的Datasheet PDF文件第48页浏览型号SI3225-FQ的Datasheet PDF文件第49页浏览型号SI3225-FQ的Datasheet PDF文件第50页  
Si3220/Si3225  
Ringing Generation  
The Si3220-based Dual ProSLIC chipset provides a  
balanced ringing waveform with or without dc offset.  
The ringing frequency, cadence, waveshape, and dc  
offset are register-programmable.  
RLOOP  
+
ROUT  
Using a balanced ringing scheme, the ringing signal is  
applied to both the TIP and the RING lines using ringing  
waveforms that are 180° out of phase with each other.  
The resulting ringing signal seen across TIP-RING is  
twice the amplitude of the ringing waveform on either  
the TIP or the RING line, which allows the ringing  
circuitry to withstand half the total ringing amplitude  
seen across TIP-RING.  
RLOAD  
VTERM  
VRING  
Figure 24. Simplified Loop Circuit During  
Ringing  
VRING  
The following equation can be used to determine the  
TIP-RING ringing amplitude required for a specific load  
and loop condition:  
RING  
VOFF  
SLIC  
TIP  
RLOAD  
(RLOAD + RLOOP + ROUT  
---------------------------------------------------------------------  
×
VTERM = VRING  
VTIP  
)
where  
GND  
RLOOP= (0.09 per foot for 26AWG wire)  
VCM  
VTIP  
V PK  
ROUT = 320 Ω  
VOFF  
and  
7000 Ω  
-------------------  
=
RLOAD  
#REN  
When ringing longer loop lengths, adding a dc offset  
voltage is necessary to reliably detect a ring trip  
condition (off-hook phone). Adding dc offset to the  
ringing signal decreases the maximum possible ringing  
amplitude. Adding significant dc offset also increases  
the power dissipation in the Si3200 and may require  
additional airflow or modified PCB layout to maintain  
acceptable operating temperatures in the line feed  
circuitry. The Dual ProSLIC chipset automatically  
VOV  
VRING  
VBATH  
Figure 23. Balanced Ringing  
An internal ringing scheme provides >40 Vrms into a 5  
REN load at the terminal equipment using a user-  
provided ringing battery supply. The specific ringing  
supply voltage required depends on the desired ringing  
voltage. The ringing amplitude at the terminal  
equipment also depends on the loop impedance and  
the load impedance in REN. The simplified circuit in  
Figure 24 shows the relationship between loop  
impedance and load impedance.  
applies and removes the ringing signal during V  
-
OC  
crossing periods to reduce noise and crosstalk to  
adjacent lines. Table 28 provides a list of registers  
required for internal ringing generation  
46  
Rev. 1.0