SiM3C1xx
Table 5.2. Pin Definitions and alternate functions for SiM3C1x6 (Continued)
Pin Name
Type
PB1.8
Standard I/O
30
29
28
27
XBR0
XBR0
XBR0
XBR0
AD14m/
A6
WAKE.2
WAKE.3
ADC1.3
CS0.12
PB1.9
PB1.10
PB1.11
Standard I/O
Standard I/O
Standard I/O
AD13m/
A5
ADC1.2
CS0.13
AD12m/
A4
DMA0T1
WAKE.4
ADC1.1
CS0.14
AD11m/
A3
DMA0T0
WAKE.5
ADC1.0
CS0.15
PMU_Asleep
PB1.12
PB1.13
PB1.14
PB1.15
PB2.0
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
Standard I/O
26
23
22
21
20
19
18
XBR0
XBR0
XBR0
XBR0
XBR1
XBR1
XBR1
AD10m/
A2
WAKE.6
AD9m/
A1
AD8m/
A0
AD7m/
D7
AD6m/
D6
LSI0 Yes
LSI1 Yes
LSI2 Yes
INT0.0
INT1.0
PB2.1
AD5m/
D5
INT0.1
INT1.1
PB2.2
AD4m/
D4
INT0.2
INT1.2
CMP0N.0
CMP1N.0
RTC0OSC_OUT
PB2.3
PB3.0
PB3.1
Standard I/O
5 V Tolerant I/O
5 V Tolerant I/O
17
16
15
XBR1
XBR1
XBR1
AD3m/
D3
LSI3 Yes
INT0.3
INT1.3
CMP0P.0
CMP1P.0
AD2m/
D2
CMP0P.1
CMP1P.1
AD1m/
D1
CMP0N.1
CMP1N.1
Preliminary Rev. 0.8
61
SILICON [ SILICON ]
