SiM3C1xx
volatile data storage and allowing field upgrades of the firmware. User firmware has complete control of all
peripherals and may individually shut down and gate the clocks of any or all peripherals for power savings.
The on-chip debugging interface (SWJ-DP) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and
modification of memory and registers, setting breakpoints, single stepping, and run and halt commands. All analog
and digital peripherals are fully functional while debugging.
Each device is specified for 1.8 to 3.6 V operation over the industrial temperature range (–40 to +85 °C). The Port
I/O and RESET pins are powered from the IO supply voltage. The SiM3C1xx devices are available in 40-pin or 64-
pin QFN, 64-pin or 80-pin TQFP, or 92-pin LGA packages. All package options are lead-free and RoHS compliant.
See Table 6.1 for ordering information. A block diagram is included in Figure 4.1.
Analog
SARADC0
IDAC0
Watchdog
Timer
(WDTIMER0)
Debug /
Programming
Hardware
Core
SARADC1
IDAC1
ARM Cortex M3
Power On Reset /
PMU
Comparator 0 Comparator 1
IVC0
Memory
Voltage Supply
32/64/128/256 kB Flash
4/12/28 kB RAM
Monitor (VMON0)
Capacitive Sensing 0
I/O
Power
4 kB retention RAM
EMIF
Low Dropout Regulator (LDO0)
Voltage Regulator (VREG0)
DMA
Crossbars
External Regulator (EXTVREG0)
Power Management Unit (PMU)
16-Channel Controller
Peripheral Crossbar
Standard I/O pins
5 V tolerant pins
High Drive pins
Clocking
Digital
Real-Time Clock (RTC0OSC)
Low Frequency Oscillator (LFOSC0)
Low Power Oscillator (LPOSC0)
External Oscillator Control (EXTOSC0)
Phase-Locked Loop (PLL0OSC)
Peripheral Clock Control (CLKCTRL)
USART0 USART1
UART0
UART1
SPI0
I2C0
SPI1
SPI2
I2C1
Clock Control
I2S0
EPCA0
PCA0
AES0
CRC0
PCA1
Timer 0
Timer 1
Low Power Timer (LPTIMER0)
DMA access available for these peripherals
Figure 4.1. Precision32™ SiM3C1xx Family Block Diagram
32
Preliminary Rev. 0.8
SILICON [ SILICON ]
